An improved logarithmic multiplier for energy-efficient neural computing
Multiplication is the most resource-hungry operation in neural networks (NNs). Logarithmic
multipliers (LMs) simplify multiplication to shift and addition operations and thus reduce the …
multipliers (LMs) simplify multiplication to shift and addition operations and thus reduce the …
On the design of logarithmic multiplier using radix-4 booth encoding
R Pilipović, P Bulić - IEEE access, 2020 - ieeexplore.ieee.org
This paper proposes an energy-efficient approximate multiplier which combines radix-4
Booth encoding and logarithmic product approximation. Additionally, a datapath pruning …
Booth encoding and logarithmic product approximation. Additionally, a datapath pruning …
On the design of iterative approximate floating-point multipliers
Approximate multipliers provide power and area-saving for error-resilient applications. In
this paper, we first propose two approximate floating-point multipliers based on two …
this paper, we first propose two approximate floating-point multipliers based on two …
Design and analysis of leading one/zero detector based approximate multipliers
Approximate multipliers are widely used in error-tolerant applications to improve circuit
performance. For signed multiplication, previous approximate Booth multipliers usually have …
performance. For signed multiplication, previous approximate Booth multipliers usually have …
State-of-art analysis of multiplier designs for image processing and convolutional neural network applications
Z Aizaz, K Khare - 2022 International Conference for …, 2022 - ieeexplore.ieee.org
Recently, due to the immense growth of computing power, image processing and
Convolutional neural networks (CNN) have regained gigantic attention because of the …
Convolutional neural networks (CNN) have regained gigantic attention because of the …
Area-Delay-Energy-Efficient Approximate Dividers Based on Piecewise Linear Fitting of Surface
C Wu, W Shi, Y Yuan, Z Zou, Z Mo… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In this paper, signed and unsigned approximate dividers based on piecewise linear fitting of
surface (PLSAD) are proposed. After extracting the exponent and mantissa of two binary …
surface (PLSAD) are proposed. After extracting the exponent and mantissa of two binary …
Low-power approximate logarithmic squaring circuit design for DSP applications
The squaring function is widely used in Digital Signal Processing (DSP). There are many
DSP applications with noisy inputs for which simplifying approximations of the squaring …
DSP applications with noisy inputs for which simplifying approximations of the squaring …
A low error, hardware efficient logarithmic multiplier
LGSS Harsha, BR Jammu, N Bodasingi… - Circuits, Systems, and …, 2022 - Springer
The ever-increasing requirement for high-performance signal processing blocks in artificial
intelligence, IoT, and neural networks has rendered the Logarithmic arithmetic as front …
intelligence, IoT, and neural networks has rendered the Logarithmic arithmetic as front …
Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding
D Windhager, L Ratschbacher, BA Moser… - arXiv preprint arXiv …, 2025 - arxiv.org
Spiking Neural Networks (SNNs) have garnered attention over recent years due to their
increased energy efficiency and advantages in terms of operational complexity compared to …
increased energy efficiency and advantages in terms of operational complexity compared to …
Efficient leading zero count (LZC) implementations for Xilinx FPGAs
Leading zero count (LZC) is a fundamental building block in floating-point arithmetic and
data sketches. These applications are increasingly being implemented on field …
data sketches. These applications are increasingly being implemented on field …