Closely packed vertical transistors with reduced contact resistance
ABSTRACT A method of forming a semiconductor device and resulting structures having
closely packed vertical transistors with reduced contact resistance by forming a …
closely packed vertical transistors with reduced contact resistance by forming a …
Methods of forming a gate structure on a vertical transistor device
JH Zhang, SJ Bentley, KY Lim - US Patent 9,799,751, 2017 - Google Patents
US9799751B1 - Methods of forming a gate structure on a vertical transistor device - Google
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction
SUMMARY InaCCOrdance WithanembOdiment Ofthe preSentinvention, amethOd
Offabricatingadjacent Vertical finSwithtOp SOurce/drainS having anair Spacerand a Self …
Offabricatingadjacent Vertical finSwithtOp SOurce/drainS having anair Spacerand a Self …
Fabrication of a vertical fin field effect transistor having a consistent channel width
K Cheng, J Li - US Patent 9,837,405, 2017 - Google Patents
ABSTRACT A method of forming a vertical fin field effect transistor having a consistent
channel width, including forming one or more vertical fin (s) on the substrate, wherein the …
channel width, including forming one or more vertical fin (s) on the substrate, wherein the …
Vertical transport FET devices with uniform bottom spacer
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents …
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents …
Methods of forming vertical transistor devices with different effective gate lengths
R Xie, CC Yeh, T Yamashita, K Cheng - US Patent 9,935,018, 2018 - Google Patents
One illustrative method disclosed herein includes, among other things, forming first and
second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and …
second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and …
Method and structure of forming self-aligned rmg gate for vfet
H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …
Air gap adjacent a bottom source/drain region of vertical transistor device
R Xie, CC Yeh, K Cheng, T Yamashita - US Patent 10,014,370, 2018 - Google Patents
One illustrative method disclosed herein includes, among other things, forming an initial
bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel …
bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel …
Vertical transistor contact for cross-coupling in a memory cell
BA Anderson, TB Hook, J Wang - US Patent 10,566,453, 2020 - Google Patents
6,137,129 A 10/2000 Bertin et al. 6,759,699 B1 7/2004 Chi 7,138,685 B2 11/2006 Hsu et al.
7,678,658 B2 3/2010 Yang et al. 8,035,170 B2 10/2011 Inaba 8,169,030 B2 5/2012 …
7,678,658 B2 3/2010 Yang et al. 8,035,170 B2 10/2011 Inaba 8,169,030 B2 5/2012 …
Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures
Disclosed are methods wherein vertical field effect transistor (s)(VFET (s)) and isolation
region (s) are formed on a substrate. Each VFET includes a fin extending vertically between …
region (s) are formed on a substrate. Each VFET includes a fin extending vertically between …