The main goal of writing this book was to present a methodological and algorithmic perspective on the field-solver-based parasitic extraction of integrated circuits (ICs) …
T El-Moselhy, L Daniel - 2011 12th International Symposium on …, 2011 - ieeexplore.ieee.org
In this paper we review some of the state of the art techniques for parasitic interconnect extraction in the presence of random geometrical variations due to uncertainties in the …
P Benner, L Feng - Model Reduction for Circuit Simulation, 2011 - Springer
We discuss the numerical solution of successive linear systems of equations Ax= b_i,\i= 1, 2, ..., m, by iterative methods based on recycling Krylov subspaces. We propose various …
SUMMARY A fast computational technique that speeds up the process of parametric macro‐ model extraction is proposed. An efficient starting point is the technique of parametric model …
Many model order reduction methods for parameterized systems need to construct a projection matrix V which requires computing several moment matrices of the parameterized …
MP Neuenhofen, C Greif - SIAM Journal on Scientific Computing, 2018 - SIAM
We introduce M stab, a Krylov subspace recycling method for the iterative solution of sequences of linear systems, where the system matrix is fixed and is large, sparse, and …
B Boghrati, SS Sapatnekar - 17th Asia and South Pacific …, 2012 - ieeexplore.ieee.org
The process of power network analysis during VLSI chip design is inherently iterative. It is very common for the designer to make many small perturbations to an otherwise complete …
For the numerical solution of ODE/PDEs that describe the basic laws of science, such as Kirchhoff's laws in circuit analysis, or nonlinear deformation equations in structural analysis …
B Boghrati, SS Sapatnekar - ACM Transactions on Design Automation of …, 2014 - dl.acm.org
Power grid design and analysis is a critical part of modern VLSI chip design and demands tools for accurate modeling and efficient analysis. The process of power grid design is …