Recent advances in state-of-the-art DNN architecture design have been moving toward
Transformer models. These models achieve superior accuracy across a wide range of …

DIgital-ANAlog (DIANA), a heterogeneous multi-core accelerator, combines a reduced
instruction set computer-five (RISC-V) host processor with an analog in-memory computing …

The rapidly-changing deep learning landscape presents a unique opportunity for building
inference accelerators optimized for specific datacenter-scale workloads. We propose Full …

In the hardware design space exploration process, it is critical to optimize both hardware
parameters and algorithm-to-hardware mappings. Previous work has largely approached …

DNN workloads can be scheduled onto DNN accelerators in many different ways: from layer-
by-layer scheduling to cross-layer depth-first scheduling (aka layer fusion, or cascaded …

Extreme edge devices or Internet-of-Things (IoT) nodes require both ultra-low power (ULP)
always-on (AON) processing as well as the ability to do on-demand sampling and …

Memory buffer allocation for on-chip memories is a major challenge in modern machine
learning systems that target ML accelerators. In interactive systems such as mobile phones …

Deep learning accelerators are important tools for feeding the growing demand for deep
learning applications. The automated design of such accelerators—which is important for …

In-memory-computing is emerging as an efficient hardware paradigm for deep neural
network accelerators at the edge, enabling to break the memory wall and exploit massive …

Map Space Exploration is the problem of finding optimized mappings of a Deep Neural
Network (DNN) model on an accelerator. It is known to be extremely computationally …