Co-packaged photonics for high performance computing: status, challenges and opportunities
R Mahajan, X Li, J Fryman, Z Zhang… - Journal of Lightwave …, 2021 - ieeexplore.ieee.org
Photonics die or integrated photonics modules co-packaged with compute engines have the
potential to deliver significant improvements in power, bandwidth and reach needed to meet …
potential to deliver significant improvements in power, bandwidth and reach needed to meet …
Co-packaged optics (CPO): status, challenges, and solutions
Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter
traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three …
traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three …
[HTML][HTML] InP photonic integrated multi-layer neural networks: Architecture and performance analysis
We demonstrate the use of a wavelength converter, based on cross-gain modulation in a
semiconductor optical amplifier (SOA), as a nonlinear function co-integrated within an all …
semiconductor optical amplifier (SOA), as a nonlinear function co-integrated within an all …
A 240 Gb/s PAM4 silicon micro-ring optical modulator
A 240 Gb/s PAM4 Silicon Micro-Ring Optical Modulator Page 1 A 240 Gb/s PAM4 Silicon
Micro-Ring Optical Modulator Meer Sakib, Ranjeet Kumar, Chaoxuan Ma, Duanni Huang, Xinru …
Micro-Ring Optical Modulator Meer Sakib, Ranjeet Kumar, Chaoxuan Ma, Duanni Huang, Xinru …
[HTML][HTML] The big chip: Challenge, model and architecture
Abstract As Moore's Law comes to an end, the implementation of high-performance chips
through transistor scaling has become increasingly challenging. To improve performance …
through transistor scaling has become increasingly challenging. To improve performance …
A 112-Gb/s—8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
D Patel, A Sharif-Bakhtiar… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect
transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4 …
transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4 …
[HTML][HTML] High-bandwidth density silicon photonic resonators for energy-efficient optical interconnects
The growth of artificial intelligence applications demands ever larger and more complex
deep learning models, dominating today's—and tomorrow's—data center and high …
deep learning models, dominating today's—and tomorrow's—data center and high …
High capacity, low power, short reach integrated silicon photonic interconnects
The architecture and component technology of a low power, high capacity, short reach
optical interconnect are detailed. Measurements from high-performance 300 mm silicon …
optical interconnect are detailed. Measurements from high-performance 300 mm silicon …
Peta-scale embedded photonics architecture for distributed deep learning applications
As Deep Learning (DL) models grow larger and more complex, training jobs are
increasingly distributed across multiple Computing Units (CU) such as GPUs and TPUs …
increasingly distributed across multiple Computing Units (CU) such as GPUs and TPUs …
Highly integrated 4 Tbps silicon photonic IC for compute fabric connectivity
S Fathololoumi, C Malouin, D Hui… - … IEEE Symposium on …, 2022 - ieeexplore.ieee.org
In this work we present the design and performance of a high bandwidth, low power, low
latency, and high-density Silicon Photonic integrated circuit (SiPIC) for compute …
latency, and high-density Silicon Photonic integrated circuit (SiPIC) for compute …