A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit,
successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise …
successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise …
A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm
This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference
buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of …
buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of …
A 10-bit 100-MS/s SAR ADC with always-on reference ripple cancellation
This work presents an always-on reference ripple cancellation technique that actively
cancels the reference settling error throughout the entire SAR conversion process. Unlike …
cancels the reference settling error throughout the entire SAR conversion process. Unlike …
A design of low-power 10-bit 1-ms/s asynchronous sar adc for dsrc application
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register
analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of …
analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of …
[HTML][HTML] Digitalized analog integrated circuits
Z Zhu, S Liu - Fundamental Research, 2023 - Elsevier
Digital integrated circuits have significantly benefited from technology scaling down, while
conventional analog integrated circuits suffer from more design constraints. In recent years …
conventional analog integrated circuits suffer from more design constraints. In recent years …
High energy efficiency and linearity switching scheme without reset energy for SAR ADC
X Tong, S Zhao, X Xin - Circuits, Systems, and Signal Processing, 2022 - Springer
A high energy efficiency and linearity switching scheme is proposed for the successive
approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching …
approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching …
A 14b 500 MS/s single-channel pipelined-SAR ADC with reference ripple mitigation techniques and adaptively biased floating inverter amplifier
This work presents a 14-bit 500 MS/s single-channel pipelined-successive-approximation-
register (SAR) analog-to-digital converter (ADC) with an adaptively biased floating inverter …
register (SAR) analog-to-digital converter (ADC) with an adaptively biased floating inverter …
Deterministic Dithering-Based 12-b 8-MS/s SAR ADC in 0.18-μm CMOS
This letter presents a 12-bit binary-weighted successive approximation register (SAR) ADC
calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch …
calibrated using self-subtractive deterministic dithering to determine the capacitor mismatch …
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
YH Tsai, SI Liu - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
A 12-bit 20-MS/s asynchronous successive approximation register (SAR) analog-to-digital
converter (ADC) is presented by using the digital place-and-route (DPR) tools. The …
converter (ADC) is presented by using the digital place-and-route (DPR) tools. The …
A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning
P Yang, F Li, Z Wang - … Transactions on Circuits and Systems II …, 2024 - ieeexplore.ieee.org
This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-
ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28nm CMOS technology and uses …
ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28nm CMOS technology and uses …