Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital
signal post-processing has drawn growing interest with technology scaling, but power …

This paper investigates the performance benefit of using nonuniformly quantized ADCs for
implementing high-speed serial receivers with decision-feedback equalization (DFE). A way …

In this paper, we propose low precision BER-optimal analog-to-digital converters (ADC)
where quantization levels and thresholds are set nonuniformly to minimize the bit-error rate …

This paper presents a 4-bit 20-GSps time-interleaved flash ADC for an ADC-based high-
speed serial-link equalizer. The ADC is designed and simulated in a 65-nm CMOS …

The design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS is
described. Accuracy requirements are met without compromising the high-speed …

This paper introduces the design of a high-speed reconfigurable analog-to-digital converter
in 65-nm CMOS. Accuracy requirements are met without compromising performance by …

This paper presents the design and analysis of a serial link transceiver (TRX) architecture
employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single …

This paper presents a 20-GSps low-power ADC-based equalizer for high speed serial links
receiver. Digital receivers are recently adopted to overcome the challenges of power, delay …

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a
front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as …

The data-rate demand in high-speed interface circuits increases exponentially every year.
High-speed I/Os are better implemented in advanced process technologies for lower-power …