One-IPC high-level simulation of microthreaded many-core architectures

I Uddin - The International Journal of High Performance …, 2017 - journals.sagepub.com
The microthreaded many-core architecture is comprised of multiple clusters of fine-grained
multi-threaded cores. The management of concurrency is supported in the instruction set …

High-level simulation of concurrency operations in microthreaded many-core architectures

I Uddin - GSTF Journal on Computing (JoC), 2015 - Springer
Computer architects are always interested in analyzing the complex interactions amongst
the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate …

[HTML][HTML] Multiple levels of abstraction in the simulation of microthreaded many-core architectures

I Uddin - Open Journal of Modelling and Simulation, 2015 - scirp.org
Simulators are generally used during the design of computer architectures. Typically,
different simulators with different levels of complexity, speed and accuracy are used …

Cache-based high-level simulation of microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - Journal of Systems Architecture, 2014 - Elsevier
The accuracy of simulated cycles in high-level simulators is generally less than the accuracy
in detailed simulators for a single-core systems, because high-level simulators simulate the …

Analytical-based high-level simulation of the microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - 2014 22nd Euromicro …, 2014 - ieeexplore.ieee.org
High-level simulation is becoming commonly used for design space exploration of many-
core systems. We have been working on high-level simulation techniques for the …

Signature-based high-level simulation of microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - 2014 4th International …, 2014 - ieeexplore.ieee.org
The simulation of fine-grained latency tolerance based on the dynamic state of the system in
high-level simulation of many-core systems is a challenging simulation problem. We have …

Architecting a pluggable query executor for emerging co-processors

B Gurumurthy - 2024 - repo.bibliothek.uni-halle.de
CPUs are reaching their scaling limitations while data keeps growing rapidly. De-velopers of
CPU-based applications are searching for an alternative processor to further improve their …

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches

Q Yang, J Fu, R Poss, C Jesshope - ACM Transactions on Embedded …, 2014 - dl.acm.org
When hardware cache coherence scales to many cores on chip, over saturated traffic of the
shared memory system may offset the benefit from massive hardware concurrency. In this …

[PDF][PDF] A highly-parallel formulation of quantum computing simulation through fine-grained dataflow

Y Vandriessche, E D'Hondt, T Van Cutsem… - Workshop on Data-Flow …, 2013 - Citeseer
Quantum Computing lies at the frontier of computing, offering a radically different and
unconventional model of computation. In the absence of practical quantum computers today …

[PDF][PDF] Automatically Parallelizing Embedded Legacy Software on Soft-Core SoCs

K Heid - 2019 - d-nb.info
Nowadays, embedded systems are utilized in many areas and become omnipresent,
making people's lives more comfortable. Embedded systems have to handle more and more …