P5: A protocol for scalable anonymous communication

R Sherwood, B Bhattacharjee… - Journal of Computer …, 2005 - content.iospress.com
We present a protocol for anonymous communication over the Internet. Our protocol, called
P 5 (Peer-to-Peer Personal Privacy Protocol) provides sender–, receiver–, and sender …

[图书][B] EDA for IC implementation, circuit design, and process technology

L Lavagno, L Scheffer, G Martin - 2018 - books.google.com
Presenting a comprehensive overview of the design automation algorithms, tools, and
methodologies used to design integrated circuits, the Electronic Design Automation for …

Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

W Chen, SK Gupta, MA Breuer - Proceedings International Test …, 1997 - ieeexplore.ieee.org
In this paper we develop a general methodology to analyze crosstalk to obtain insight into
effects that are likely to cause errors in deep submicron high speed circuits. We focus on …

Test generation for crosstalk-induced delay in integrated circuits

WY Chen, SK Gupta, MA Breuer - … Test Conference 1999 …, 1999 - ieeexplore.ieee.org
Due to technology scaling and increasing clock frequency, problems due to noise effects
lead to an increase in design/debugging efforts and a decrease in circuit performance. This …

CAD-Base: An attack vector into the electronics supply chain

K Basu, SM Saeed, C Pilato, M Ashraf… - ACM Transactions on …, 2019 - dl.acm.org
Fabless semiconductor companies design system-on-chips (SoC) by using third-party
intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy …

Test generation in VLSI circuits for crosstalk noise

W Chen, SK Gupta, MA Breuer - Proceedings International Test …, 1998 - ieeexplore.ieee.org
This paper addresses the problem of efficiently and accurately generating two-vector tests
for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital …

Towards true crosstalk noise analysis

P Chen, K Keutzer - … on Computer-Aided Design. Digest of …, 1999 - ieeexplore.ieee.org
Accurate noise analysis is currently of significant concern to high-performance designs, and
the number of signals susceptible to noise effects will certainly increase in smaller process …

[PDF][PDF] A novel VLSI layout fabric for deep sub-micron applications

SP Khatri, A Mehrotra, RK Brayton… - Proceedings of the 36th …, 1999 - dl.acm.org
We propose a new VLSI layout methodology which addresses the main problems faced in
Deep Sub-Micron (DSM) integrated circuit design. Our layout “fabric” scheme eliminates the …

Delay testing considering crosstalk-induced effects

A Krstic, JJ Liou, YM Jiang… - … Test Conference 2001 …, 2001 - ieeexplore.ieee.org
Increased noise/interference effects, such as crosstalk, power supply noise, substrate noise
and distributed delay variations lead to increased signal integrity problems in deep …

Process variations and their impact on circuit operation

S Natarajan, MA Breuer… - Proceedings 1998 IEEE …, 1998 - ieeexplore.ieee.org
The statistical variations in electrical parameters, such as transistor gain factors and
interconnect resistances, due to variations in the manufacturing process are studied using …