The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based
frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques
exploiting a sub-sampling phase detector (SSPD)(which is also referred to as a sampling …

The high phase noise of ring oscillators has generally discouraged their use in RF synthesis.
This paper introduces an integer-N synthesizer that employs a type-I loop to achieve a wide …

Nonlinearities in the time-to-digital converter (TDC) are a significant source of fractional
spurs in a divider-less fractional-N ADPLL. Using an abstract model for the TDC, this paper …

A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137-and 142-fs rms
jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz, respectively. With a …

A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented
which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop …

Microwave biosensor shows great potential in mediator-free glucose detection. However,
most microwave biosensors are passive devices; therefore, the high-stability and SNR …

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization
technique to improve the performance of a delta-sigma (ΔΣ) fractional-N PLL. The proposed …

A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …

Sub-sampling phase detectors (SSPDs) have recently been demonstrated to enable phase-
locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes …