An exponential rise in transistor count, have increased the power consumption of the
modern digital system. Moreover, at lower technology node, the performance of …

During recent years, high-k spacer materials have been extensively studied for the
enhancement of electrostatic control and suppression of short-channel effects in nanoscaled …

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the
best candidates for ultimately scaled CMOS devices at the end of the technology roadmap …

We present a model for estimating the impact of gate line edge roughness (LER) on the
performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG …

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET)
structure using a dual-k spacer. Asymmetric dual-spacer at source shows excellent gate …

The main purpose of this paper is to achieve as low as possible leakage current (I OFF) to
meet the requirements for ultra-low power (ULP) applications. The proposed methodology is …

A new FinFET memory circuit technique based on asymmetrically gate underlap engineered
bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline …

This study for the first time uses a 3nm technology node (N3) Bi-Level Negative capacitance
FET (BLNC-FET) to examine the influence of symmetric underlap ferroelectric dual-k spacer …

This book presents the material necessary for understanding the physics, operation, design,
and performance of modern MOSFETs with nanometer dimensions. It offers a brief …

Multigate structures have better short channel control than conventional bulk devices due to
increased gate electrostatic control. FinFET is a promising candidate among multigate …