Multi-modal data-driven clock recovery circuit

A Tajalli, A Hormati - US Patent 10,693,473, 2020 - Google Patents
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input comparator …

Measurement and correction of multiphase clock duty cycle and skew

MA Ashtiani, K Gharibdoust - US Patent 10,630,272, 2020 - Google Patents
Methods and systems are described for generating, at a plurality of delay stages of a local
oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal …

Multi-modal data-driven clock recovery circuit

A Tajalli, A Hormati - US Patent 11,271,571, 2022 - Google Patents
Multi-mode non-return-to-zero (NRZ) and orthogonal dif ferential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input com parator …

Thermometer code generator, and frequency-locked loop including the same

IH Lee, SS Yoon, YH Kwak, KH Kim, C Kim - US Patent 7,639,086, 2009 - Google Patents
(57) ABSTRACT A thermometer code generator includes n bit storing stages that are
coupled to each other, where n is an integer greater than 1, and the n bit storing stages store …

Quadrature voltage controlled oscillators with phase shift detector

E Metaxakis - US Patent 7,271,622, 2007 - Google Patents
In Wireless application there is made use of a quadrature oscillators that generate signals
that are capable of oscillat ing at quadrature of each other. The quadrature oscillator is …

High performance phase locked loop

A Tajalli - US Patent 10,374,787, 2019 - Google Patents
Methods and systems are described for receiving N phases of a local clock signal and M
phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an …

Clock-and-data recovery (CDR) circuitry for performing automatic rate negotiation

A Yadav, S Aboulhouda, F Chaahoub - US Patent 10,348,414, 2019 - Google Patents
A CDR circuit for use in an optical receiver is provided that performs automatic rate
negotiation. The CDR circuit is configured to determine whether the incoming data signal …

Parametric measurement of high-speed I/O systems

HS Wallace, AWC Seet, KD Hilliges - US Patent 7,571,363, 2009 - Google Patents
(57) ABSTRACT A phase comparator is used to test a device under test com prising an
input/output (I/O) circuit by applying a signal to the device under test; extracting a phase …

Clock and data recovery circuit with decision feedback equalization

J Savoj - US Patent 8,472,515, 2013 - Google Patents
A phase detection and decision feedback equalization circuit is provided. A first latch and a
second latch are coupled to an input of the circuit. A third latch and a fourth latch are …

Linear phase interpolation circuit

OT Amiri, A Tajalli - US Patent 10,488,227, 2019 - Google Patents
Methods and systems are described for receiving a control step input at a binary-to-
thermometer decoder and responsively generating bits of a thermometer codeword …