Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: Industrial product

C Chen, X Xiang, C Liu, Y Shang, R Guo… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
The open source RISC-V ISA has been quickly gaining momentum. This paper presents
Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from …

A RISC-V instruction set processor-micro-architecture design and analysis

A Raveendran, VB Patil, D Selvakumar… - … Conference on VLSI …, 2016 - ieeexplore.ieee.org
Micro-architecture design and analysis of a RISC-V instruction set processor has been
articulated in this paper. Instruction Set Architectures (ISAs) for processors from Intel, AMD …

Software‐Defined Radio FPGA Cores: Building towards a Domain‐Specific Language

L Tsoeunyane, S Winberg… - International Journal of …, 2017 - Wiley Online Library
This paper reports on the design and implementation of an open‐source library of
parameterizable and reusable Hardware Description Language (HDL) Intellectual Property …

Design and implementation of an OpenRISC system-on-chip with an encryption peripheral

L Akcay, M Tukel, B Ors - 2017 European Conference on …, 2017 - ieeexplore.ieee.org
Open source hardware projects are becoming more and more common. OpenRISC SOC,
one of the prominent of these projects, has become quite popular with the support of …

Microarchitecture based RISC-V Instruction Set Architecture for Low Power Application

R Deepika, GP SM, V Anand - Journal of Pharmaceutical …, 2022 - pnrjournal.com
The goal of many contemporary and speculative applications is to create highly efficient
CPUs and one among the architecture that is meeting out the above said condition is RISC …

Research on Instruction Pipeline Optimization Oriented to RISC-V Vector Instruction Set

Z Zhang, X Yu - International Conference on Artificial Intelligence and …, 2022 - Springer
Traditional general-purpose processors are scalar processors, and only one data result is
obtained when an instruction is executed. But nowadays, there are a lot of data parallel …

[PDF][PDF] Enhancing the RISC-V instruction set architecture

P Petrov - 2019 - project-archive.inf.ed.ac.uk
Since its emergence, RISC-V has offered a license-free alternative to proprietary instruction
sets designed by ARM and Intel by providing a stable base to researchers and small …

SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios

LJ Tsoeunyane - 2020 - open.uct.ac.za
Abstract Modern design of Software-Defined Radio (SDR) applications is based on Field
Programmable Gate Arrays (FPGA) due to their ability to be configured into solution …

Development and testing of the RHINO host streamed data acquisition framework

M Boleme - 2017 - open.uct.ac.za
This project focuses on developing a supporting framework for integrating the
Reconfigurable Hardware INterface for computing and radiO (RHINO) with a Personal …

RHINO software-defined radio processing blocks

LJ Tsoeunyane - 2015 - open.uct.ac.za
This MSc project focuses on the design and implementation of a library of parameterizable,
modular and reusable Digital IP blocks designed around use in Software-Defined Radio …