[PDF][PDF] Improving characteristics of LUT-based Mealy FSMs

A Barkalov, L Titarenko… - International Journal of …, 2020 - intapi.sciendo.com
Practically, any digital system includes sequential blocks represented using a model of finite
state machine (FSM). It is very important to improve such FSM characteristics as the number …

An application of functional decomposition in ROM-based FSM implementation in FPGA devices

M Rawski, H Selvaraj, T Łuba - Journal of Systems Architecture, 2005 - Elsevier
Modern FPLD devices have very complex structure. They combine PLA like structures, as
well as FPGA and even memory-based structures. However lack of appropriate synthesis …

Area–oriented technology mapping for LUT–based logic blocks

M Kubica, D Kania - International Journal of Applied Mathematics and …, 2017 - sciendo.com
One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology
mapping, which is directly associated with the logic decomposition technique. This paper …

Methods of improving time efficiency of decomposition dedicated at FPGA structures and using BDD in the process of cyber-physical synthesis

A Opara, M Kubica, D Kania - IEEE Access, 2019 - ieeexplore.ieee.org
Physical systems may be carried out in both hardware and software. Hardware is based on
implementing appropriate logic functions in FPGA structures connected with a physical layer …

Strategy of logic synthesis using MTBDD dedicated to FPGA

A Opara, M Kubica, D Kania - Integration, 2018 - Elsevier
The paper presents a synthesis strategy oriented to the implementation of multi-output
functions into LUT-based FPGA. The key elements of the proposed method include the …

SMTBDD: new form of BDD for logic synthesis

M Kubica, D Kania - International Journal of Electronics and …, 2016 - infona.pl
The main purpose of the paper is to suggest a new form of BDD-SMTBDD diagram, methods
of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of …

Decomposition approaches for power reduction

A Opara, M Kubica, D Kania - IEEE Access, 2023 - ieeexplore.ieee.org
The article discusses a synthesis strategy aimed at reducing power consumption consumed
by logic structures implemented in FPGAs. The essence of the method is to carry out …

Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures

M Rawski, L Jóźwiak, T Łuba - Journal of Systems Architecture, 2001 - Elsevier
The functional decomposition of binary and multi-valued discrete functions and relations has
been gaining more and more recognition. It has important applications in many fields of …

Design and Optimization of a Petri Net-Based Concurrent Control System toward a Reduction in the Resources in a Field-Programmable Gate Array

R Wiśniewski, A Opara, M Wojnakowski - Applied Sciences, 2024 - mdpi.com
A novel design technique of a Petri net-based concurrent control system is proposed in this
paper. The idea is oriented on the effective implementation of the system within the FPGA …

[PDF][PDF] Comparison of the hardware performance of the AES candidates using reconfigurable hardware

PR Chodowiec, K Gaj - 2002 - pdfs.semanticscholar.org
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable
Hardware Page 1 Pawel Chodowiec MS CpE Candidate, ECE George Mason University …