A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture
W El-Halwagy, A Nag, P Hisayasu… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …
A Low-Noise Fractional- Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications
In this paper, we propose a 60-GHz fractional-digital frequency synthesizer aimed at
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
Low-power and low-noise millimeter-wave SSPLL with subsampling lock detector for automatic dividerless frequency acquisition
An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a …
A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of− 256 dB
DG Lee, PP Mercier - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …
A fully integrated 0.27-THz injection-locked frequency synthesizer with frequency-tracking loop in 65-nm CMOS
A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …
NSRR microwave sensor based on PLL technology for glucose detection
X Fu, J Wu, X Wang, X Gu, C Wang… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Microwave biosensor shows great potential in mediator-free glucose detection. However,
most microwave biosensors are passive devices; therefore, the high-stability and SNR …
most microwave biosensors are passive devices; therefore, the high-stability and SNR …
Analysis and design of coupled pll-based cmos quadrature vcos
A novel architecture to implement quadrature voltage-controlled oscillators (QVCOs), based
on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution …
on the coupled phase-locked loop (CPLL) technique, is presented. The proposed solution …
A charge-sharing locking technique with a general phase noise theory of injection locking
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …