Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed
acyclic graphs. They form a canonical representation, making testing of functional properties …

Valiant (1984) and others have studied the problem of learning various classes of Boolean
functions from examples. Here we discuss incremental learning of these functions. We …

In recent years, formal methods have emerged as an alternative approach to ensuring the
quality and correctness of hardware designs, overcoming some of the limitations of …

Formal Equivalence Checking and Design Debugging covers two major topics in design
verification: logic equivalence checking and design debugging. The first part of the book …

This paper presents CirFix, a framework for automatically repairing defects in hardware
designs implemented in languages like Verilog. We propose a novel fault localization …

In the process of VLSI design, specifications are often changed. It is desirable that such
changes will not lead to a very di erent design so that a large part of engineering e ort can …

The emergence of multimedia and high-speed networks has expanded the class of
applications that combine the timing requirements of hard real-time applications with the …

With the increase in the complexity of digital VLSI circuit design, logic design errors can
occur during synthesis. In this paper, we present a test vector simulation-based approach for …

A small change in the input to logic synthesis may cause a large change in the output
implementation. This is undesirable if a designer has some investment in the old …

We present RTL-Repair, a semantics-based repair tool for register transfer level circuit
descriptions. Compared to the previous state-of-the-art tool, RTL-Repair generates more …