Abstract Model checking is an automatic technique for verifying finite-state reactive systems,
such as sequential circuit designs and communication protocols. Specifications are …

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is
modified to represent state graphs using binary decision diagrams (BDD's) and partitioned …

Temporal logic model checking is an automatic technique for verifying finite-state concurrent
systems. Specifications are expressed in a propositional temporal logic, and the concurrent …

We significantly reduce the complexity of BDD-based symbolic verification by using
partitioned transition relations to represent state transition graphs. On an example pipeline …

The Forte formal verification environment for datapath-dominated hardware is described.
Forte has proven to be effective in large-scale industrial trials and combines an efficient …

Abstract esterel is a synchronous concurrent programming language dedicated to reactive
systems (controllers, protocols, man-machine interfaces etc.). esterel has an efficient …

In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP.
RASP consists of a core with a set of synthesis and optimization algorithms for technology …

Functional dependency is concerned with rewriting a Boolean function f as a function h over
a set of base functions {g 1,..., gn), ie f= h (g 1,..., gn). It plays an important role in many …

We present a new way to define the semantics of imperative synchronous languages by
means of separating the control and the data flow. The control flow is defined by predicates …

This paper describes a system for designing and implementing controllers for structured
data processing. A graphical input style describes the format of the data to be processed …