This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially
improves the resiliency of STT-MRAMs against variations in read accesses based on bitline …

Read access in STT-MRAMs is well known to be highly sensitive to process variations. Such
variations are responsible for read bit error rates that are worse than conventional CMOS …

This paper presents an effective approach for implementing content address memory (CAM)
based on Nonvolatile random-access memory (NV-RAM) technologies. We used the 2T-2R …

A method of providing a reference voltage for reading of a resistive memory array, and a
read circuit for reading of a resistive memory array. The method comprises the steps of …

In this paper we show that the area optimization of STT-MRAM bitcells can deliver a
substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is …

STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) is a potential
candidate for the requirement of many IoT and wearable device, which thanks to its fast write …