Concurrent error detection (CED) techniques (based on hardware duplication, parity codes,
etc.) are widely used to enhance system dependability. All CED techniques introduce some …

In this paper, a new paradigm for designing logic circuits with concurrent error detection
(CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of …

This paper proposes a new class of codes termed" weight-based codes" where each output
bit is assigned a weight and the check bits represent the stem of the weights of the output …

В книге рассматриваются коды с суммированием, при построении которых
предварительно устанавливается неравноправие между разрядами информационных …

This paper explains the concept of" modulo weight-based codes" and presents an efficient
scheme for concurrent error detection of arbitrary multilevel circuits based on these codes. It …

Systematic codes with simple formation rules and low redundancy are used in the reliable
digital systems design. Codes with summation with a constant number of check bits, which …

Представленная книга содержит в себе начальные сведения из области теории
надежности и технической диагностики устройств и систем автоматики и …

A detailed analysis of error controlled divisible codes' building techniques was carried out,
aimed at error detection in data vectors, which relate to summation codes' class. Summation …

We propose a method for learning using a set of feature representations which retrieve
different amounts of information at different costs. The goal is to create a more efficient …

A new synthesis technique for designing finite state machines with on-line parity checking is
presented. The output logic and the next-state logic of the finite state machines are checked …