Current-mode full-duplex transceiver for lossy on-chip global interconnects
N Wary, P Mandal - IEEE Journal of Solid-State Circuits, 2017 - ieeexplore.ieee.org
This paper presents an energy efficient full-duplex (FD) current-mode transceiver for on-chip
global interconnects. As it shares the same signaling port for transmitting and receiving …
global interconnects. As it shares the same signaling port for transmitting and receiving …
Reducing serial I/O power in error-tolerant applications by efficient lossy encoding
P Stanley-Marbell, M Rinard - Proceedings of the 53rd Annual Design …, 2016 - dl.acm.org
Transferring data between integrated circuits (ICs) accounts for an important fraction of the
power dissipation in wearable and mobile systems. Reducing signal transitions reduces the …
power dissipation in wearable and mobile systems. Reducing signal transitions reduces the …
An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS
This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long
distance interconnects in the mm range within MPSoCs. Its source synchronous clocking …
distance interconnects in the mm range within MPSoCs. Its source synchronous clocking …
A 0.385-pJ/bit 10-Gb/s TIA-terminated di-code transceiver with edge-delayed equalization, ECC, and mismatch calibration for HBM interfaces
The bandwidth of parallel DRAM I/O has increased to meet big-data requirements. High
bandwidth memory (HBM) interfaces use up to 1024 pins, and with an increased clock …
bandwidth memory (HBM) interfaces use up to 1024 pins, and with an increased clock …
SBCT-NoC: Ultra low-power and reliable simultaneous bi-directional current-mode transceiver for network-on-chip interconnects
R Abbasi, V Jamshidi - IEEE Transactions on Nanotechnology, 2022 - ieeexplore.ieee.org
The performance of Network-on-Chip depends a lot on the routers and interconnect circuits
used in them. The gradual movement of technology towards nanometer scales has …
used in them. The gradual movement of technology towards nanometer scales has …
Current-mode simultaneous bidirectional transceiver for on-chip global interconnects
N Wary, P Mandal - 2015 6th Asia Symposium on Quality …, 2015 - ieeexplore.ieee.org
A new current-mode simultaneous bidirectional transceiver for high speed asynchronous
communication over on-chip global interconnects has been proposed in this paper. The new …
communication over on-chip global interconnects has been proposed in this paper. The new …
An 11 Gb/s 0.376 pJ/bit Capacitor-less Dicode Transceiver with Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces
This paper presents a capacitor-less dicode transceiver with pattern-dependent
equalizations for parallel DRAM interfaces. The dicode signaling with dc-coupled …
equalizations for parallel DRAM interfaces. The dicode signaling with dc-coupled …
A self-biased current-mode amplifier with an application to 10-bit pipeline ADC
S Choi, Y Suh, J Lee, J Kim, B Kim… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-
capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a …
capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a …
[PDF][PDF] Design and implementation of triplication error correction using hamming code
L Priyadharshini, PN Krishnan, K Nandhini - 2023 - iijsr.com
Advanced electrical circuits are very concerned about error-free communication. Information
mistakes that happen during transmission may result in incorrect information being received …
mistakes that happen during transmission may result in incorrect information being received …
A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections
A Ebrahimi Jarihani, J Sturm… - International Journal of …, 2021 - Wiley Online Library
This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip
wireline communications. A MOS hybrid transistor is utilized to split the received data from …
wireline communications. A MOS hybrid transistor is utilized to split the received data from …