This paper introduces different classes of analog-to-digital converter (ADC) architecture that
non-uniformly samples the analog input and shifts from conventional voltage quantization to …

This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with
feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is …

This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with
calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient …

Parasitic coupling between the building blocks within a fractional-N phase-locked loop (PLL)
can result in noticeable spurs in its output spectrum, thus affecting the PLL's usability in …

Abstract This paper presents a 1.9-ps 8× phase interpolation time-todigital converter (PI-
TDC). This architecture enhances the resolution and conversion speed in cooperation with …

In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-
based quadrature receivers is presented. The proposed technique operates in background …

This paper introduces a different class of ADC architecture that non-uniformly samples the
analog input but generates uniform digital output. The proposed non-uniform sampling ADC …

In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are
summarized. The attention is paid to the recently proposed digital-to-time converter (DTC) …

The incessant demand for higher integration level and lower production cost has driven mm-
wave electronics to be implemented in complementary metal-oxide semiconductors …

High-speed ADCs with 6~ 10-bit resolution and multi-gigahertz sampling rate are highly
demanded in next generation wireless and wireline communication systems. For the …