A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS
A single-loop referenceless clock and data recovery (CDR) with a compact frequency
acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is …
acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is …
A sub-0.25-pJ/bit 47.6-to-58.8-Gb/s reference-less FD-less single-loop PAM-4 bang-bang CDR with a deliberate-current-mismatch frequency acquisition technique in …
This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR)
circuit without the need of reference and frequency detector (FD). Specifically, we propose a …
circuit without the need of reference and frequency detector (FD). Specifically, we propose a …
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 …
This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR)
circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate …
circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate …
The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications
In this paper three delay cell structures used in four-stage ring oscillator are evaluated. In the
first structure, the control voltage is employed to the gate of PMOS transistors which are …
first structure, the control voltage is employed to the gate of PMOS transistors which are …
A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure
In this paper, two novel architectures for circuit-level implementation of differential phase
frequency detector (PFD) have been presented. Proposed in differential and pseudo …
frequency detector (PFD) have been presented. Proposed in differential and pseudo …
A 10.8-to-37.4 Gb/s reference-less FD-less single-loop quarter-rate bang-bang clock and data recovery employing deliberate-current-mismatch wide-frequency …
This paper reports a reference-less frequency-detector-less single-loop bang-bang clock
and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current …
and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current …
A 0.32–2.7 Gb/s reference-less continuous-rate clock and data recovery circuit with unrestricted and fast frequency acquisition
NH Tho, HJ Lee, TJ An, JK Kang - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate
reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency …
reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency …
High‐speed, low power, and dead zone improved phase frequency detector
Design of a novel phase frequency detector (PFD) has been presented here. The innovative
advantage of the proposed structure is its improved dead zone performance due to the …
advantage of the proposed structure is its improved dead zone performance due to the …
A 0.8-to-6.5 Gb/s continuous-rate reference-less digital CDR with half-rate common-mode clock-embedded signaling
This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit
that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking …
that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking …
A 5.4-Gb/s, 0.57-pJ/bit, single-loop referenceless CDR with an unlimited bilateral frequency detection scheme
This article proposes a single-loop referenceless clock and data recovery (CDR) with a
bilateral bang-bang phase and frequency detector (BBPFD). The CDR achieves an …
bilateral bang-bang phase and frequency detector (BBPFD). The CDR achieves an …