Introduction to Security and Privacy on the Blockchain

H Halpin, M Piekarska - 2017 IEEE European symposium on …, 2017 - ieeexplore.ieee.org
The blockchain has fueled one of the most enthusiastic bursts of activity in applied
cryptography in years, but outstanding problems in security and privacy research must be …

Compiling for reconfigurable computing: A survey

JMP Cardoso, PC Diniz, M Weinhardt - ACM Computing Surveys (CSUR …, 2010 - dl.acm.org
Reconfigurable computing platforms offer the promise of substantially accelerating
computations through the concurrent nature of hardware structures and the ability of these …

The Chimaera reconfigurable functional unit

S Hauck, TW Fry, MM Hosler… - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
By strictly separating reconfigurable logic from the host processor, current custom computing
systems suffer from a significant communication bottleneck. In this paper, we describe …

CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit

ZA Ye, A Moshovos, S Hauck, P Banerjee - ACM SIGARCH computer …, 2000 - dl.acm.org
Reconfigurable hardware has the potential for significant performance improvements by
providing support for application-specific operations. We report our experience with …

Reconfigurable architectures for general-purpose computing

A DeHon - 1996 - dspace.mit.edu
General-purpose computing devices allow us to (1) customize computation after fabrication
and (2) conserve area by reusing expensive active circuitry for different functions in time. We …

A high-performance microarchitecture with hardware-programmable functional units

R Razdan, MD Smith - Proceedings of the 27th annual international …, 1994 - dl.acm.org
This paper explores a novel way to incorporate hardware-programmable resources into a
processor microarchitecture to improve the performance of general-purpose applications …

[PDF][PDF] DPGA utilization and application

A DeHon - Proceedings of the 1996 ACM fourth international …, 1996 - dl.acm.org
Abstract Dynamically Programmable Gate Arrays (DPGAs) are programmable arrays which
allow the strategic reuse of limited resources. In so doing, DPGAs promise greater capacity …

Bidwidth analysis with application to silicon compilation

M Stephenson, J Babb, S Amarasinghe - ACM SIGPLAN Notices, 2000 - dl.acm.org
This paper introduces Bitwise, a compiler that minimizes the bitwidth the number of bits used
to represent each operand for both integers and pointers in a program. By propagating 70 …

System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization

MA Baxter - US Patent 5,794,062, 1998 - Google Patents
A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose
Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time …

DPGA-coupled microprocessors

A DeHon, M Bolotski, TF Knight Jr - US Patent 6,052,773, 2000 - Google Patents
57 ABSTRACT A Single chip microprocessor or memory device has repro grammable
characteristics according to the invention. In the case of the microprocessor, a fixed …