Investigating the impact of logic and circuit implementation on full adder performance
This paper presents the design and characterization of 12 full-adder circuits in the IBM 90-
nm process. These include three new full-adder circuits using the recently proposed split …
nm process. These include three new full-adder circuits using the recently proposed split …
Constant delay logic style
A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-
speed applications. The CD characteristic of this logic style regardless of the logic type …
speed applications. The CD characteristic of this logic style regardless of the logic type …
Energy efficient self-adaptive Dual Mode Logic address decoder
K Vicuña, C Mosquera, A Musello, S Benedictis… - Electronics, 2021 - mdpi.com
This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode
Logic (DML) design style to allow working in two modes of operation (ie, dynamic for high …
Logic (DML) design style to allow working in two modes of operation (ie, dynamic for high …
SET tolerant dynamic logic
X She, N Li, DO Erstad - IEEE Transactions on Nuclear Science, 2012 - ieeexplore.ieee.org
This paper presents three SET tolerant dynamic logic circuits. The first one uses redundant
PMOS transistors in the precharge circuit and dual redundant pull down networks in the …
PMOS transistors in the precharge circuit and dual redundant pull down networks in the …
A low-power circuit technique for domino CMOS logic
P Meher, KK Mahapatra - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
Dynamic logic style is used in high performance circuit design because of its fast speed and
less transistors requirement as compared to CMOS logic style. But it is not widely accepted …
less transistors requirement as compared to CMOS logic style. But it is not widely accepted …
Design and evaluation of high-performance processing elements for reconfigurable systems
SS Purohit, SR Chalamalasetti… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, we present the design and evaluation of two new processing elements for
reconfigurable computing. We also present a circuit-level implementation of the data paths …
reconfigurable computing. We also present a circuit-level implementation of the data paths …
Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique
IC Wey, CW Chang, YC Liao… - International Journal of …, 2015 - Wiley Online Library
In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design
for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter …
for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter …
[PDF][PDF] High performance Adder Circuit in VLSI system
M Sentamilselvi, P Mahendran - International Journal of Technology …, 2014 - Citeseer
In VLSI system. The integrated circuit design has important role. The various parameters are
considering for design the circuit. The important parameters are power and delay. The …
considering for design the circuit. The important parameters are power and delay. The …
Performance Analysis of Full Adder based on Domino Logic Technique
In modern VLSI area efficient devices are most used because most of the devices are
becoming portable. The Domino logic techniqueis often employed in designing the area …
becoming portable. The Domino logic techniqueis often employed in designing the area …
[PDF][PDF] Design and analysis of novel high performance CMOS domino-logic for high speed applications
RK Patjoshi, CH Suvarsha, SKI Ali, SKM Basha… - ARPN J Eng Appl …, 2017 - academia.edu
Dynamic logic style is popular due to its fast processing speed and less power dissipation in
high performance circuit design as compared to static complementary metal-oxide …
high performance circuit design as compared to static complementary metal-oxide …