High-level synthesis design space exploration: Past, present, and future
BC Schafer, Z Wang - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
This article presents a survey of the different modern high-level synthesis (HLS) design
space exploration (DSE) techniques that have been proposed so far to automatically …
space exploration (DSE) techniques that have been proposed so far to automatically …
[PDF][PDF] HIFSuite: Tools for HDL code conversion and manipulation
HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support
for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL …
for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL …
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration
The consideration of an embedded device's power consumption and its management is
increasingly important nowadays. Currently, it is not easily possible to integrate power …
increasingly important nowadays. Currently, it is not easily possible to integrate power …
Veriintel2c: abstracting rtl to c to maximize high-level synthesis design space exploration
A Mahapatra, BC Schafer - Integration, 2019 - Elsevier
The design of integrated circuits (ICs) is typically done using low level Hardware Description
Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full …
Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full …
A method to abstract rtl ip blocks into c++ code and enable high-level synthesis
We present a method to automatically generate a synthesizable C++ specification from the
given RTL design of an IP block, by abstracting away most of its micro-architectural …
given RTL design of an IP block, by abstracting away most of its micro-architectural …
Mirror: Maximizing the re-usability of rtl through rtl to c compiler
MI Rashid, BC Schafer - 2023 Design, Automation & Test in …, 2023 - ieeexplore.ieee.org
This work presents a RTL to C compiler called MIRROR that maximizes the re-usability of
the generated C code for High-Level Synthesis (HLS). The uniqueness of the compiler is …
the generated C code for High-Level Synthesis (HLS). The uniqueness of the compiler is …
Abstraction of RTL IPs into embedded software
High performance provided by multi-processor System-on-Chips (MPSoCs) often induces
designers to choose customized processors to execute specific functions rather than using …
designers to choose customized processors to execute specific functions rather than using …
Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis
MI Rashid, BC Schafer - IEEE Transactions on Computer-Aided …, 2024 - ieeexplore.ieee.org
Designing Hardware at the Register Transfer level (RTL) using low-level Hardware
Description Languages (HDLs) like Verilog or VHDL gives designers large degrees of …
Description Languages (HDLs) like Verilog or VHDL gives designers large degrees of …
Detecting and analyzing code clones in HDL
K Uemura, A Mori, K Fujiwara, E Choi… - 2017 IEEE 11th …, 2017 - ieeexplore.ieee.org
In this paper, we study code clones in hardware description languages (HDLs) in
comparison with general programming languages. For this purpose, we have developed a …
comparison with general programming languages. For this purpose, we have developed a …
From RTL IP to functional system-level models with extra-functional properties
The paper presents a novel abstraction methodology for generating time-and power-
annotated TLM models from synthesizable RTL descriptions. The proposed techniques …
annotated TLM models from synthesizable RTL descriptions. The proposed techniques …