Distributed arithmetic architectures for fir filters-a comparative review

G NagaJyothi, S SriDevi - 2017 International conference on …, 2017 - ieeexplore.ieee.org
Finite impulse response (FIR) filter is an influential block in various signal processing
applications. The complexities in VLSI implementation of FIR filters is dominated by the …

Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter

SY Park, PK Meher - … Transactions on Circuits and Systems II …, 2014 - ieeexplore.ieee.org
This brief presents efficient distributed arithmetic (DA)-based approaches for high-
throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter …

FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic

PK Meher, S Chandrasekaran… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
In this paper, we present the design optimization of one-and two-dimensional fully pipelined
computing structures for area-delay-power-efficient implementation of finite-impulse …

A high-performance FIR filter architecture for fixed and reconfigurable applications

BK Mohanty, PK Meher - IEEE transactions on very large scale …, 2015 - ieeexplore.ieee.org
Transpose form finite-impulse response (FIR) filters are inherently pipelined and support
multiple constant multiplications (MCM) technique that results in significant saving of …

High performance hardware design of compressor adder in DA based FIR filters for hearing aids

SR Rammohan, N Jayashri, MA Bivi, CK Nayak… - International Journal of …, 2020 - Springer
Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the
different types of hearing loss, it is necessary to selectively amplify sounds at required …

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

BK Mohanty, PK Meher, SK Singhal, MNS Swamy - Integration, 2016 - Elsevier
In this paper, we have analyzed the register complexity of direct-form and transpose-form
structures of FIR filter and explored the possibility of register reuse. We find that direct-form …

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

G NagaJyothi, S Sridevi - Multimedia Tools and Applications, 2019 - Springer
In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out
using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission …

Design of very high-speed pipeline FIR filter through precise critical path analysis

SM Cho, PK Meher, LTN Trung, HJ Cho, SY Park - ieee access, 2021 - ieeexplore.ieee.org
In this paper, we propose a new hardware architecture of a very high-speed finite impulse
response (FIR) filter using fine-grained seamless pipelining. The proposed full-parallel …

High speed low area OBC DA based decimation filter for hearing aids application

G NagaJyothi, S Sridevi - International Journal of Speech Technology, 2020 - Springer
This brief presents a decimation filter for hearing aid application using distributed arithmetic
(DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA …

FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

J Xie, J He, G Tan - Microelectronics journal, 2010 - Elsevier
This paper presents the design optimization of fully pipelined architectures for area-time-
power-efficient implementation of finite impulse response (FIR) filter. The architectures are …