Transistor level circuit simulator using hierarchical data

A Tcherniaev, I Feinberg, W Chan, JF Tuan… - US Patent …, 2003 - Google Patents
Methods and apparatus for generating a hierarchical representation of a circuit include
obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits …

Method for supply voltage drop analysis during placement phase of chip design

JM Cohn, J Venuto, IL Wemple… - US Patent 6,523,154, 2003 - Google Patents
Panda et al.,“Model and Analysis for Combined Package and On-chip Power Grid
Simulation”, IEEE Proceedings of the 2000 International Symposium on Lower Power Elec …

Method and system for validating a hierarchical simulation database

BW Mcgaughy, J Kong - US Patent 7,434,183, 2008 - Google Patents
Abstract System and method for validating a circuit for simulation are disclosed. The system
includes at least one processing unit for executing computer programs, a graphical user …

Method for symbolic simulation of circuits having non-digital node voltages

CB McDonald, H Chou, S Gupta - US Patent 7,818,158, 2010 - Google Patents
BACKGROUND Symbolic simulation is a well-known technology for the functional
verification of digital circuits. Symbolic simula tion differs from conventional simulation in that …

Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure

BW Mcgaughy - US Patent 7,257,525, 2007 - Google Patents
(57) ABSTRACT A method for simulating a circuit includes representing the circuit as a
hierarchically arranged set of branches, including a root branch and a plurality of other …

Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure

BW Mcgaughy - US Patent 7,415,403, 2008 - Google Patents
(57) ABSTRACT A method for simulating analog behavior of a circuit in a simulation system
includes representing the circuit as a hier archically arranged set of branches, which …

System and method for simulating circuits using inline subcircuits

DJ O'riordan, WJ Ghijsen, KS Kundert - US Patent 6,381,563, 2002 - Google Patents
(57) ABSTRACT A System and method for generating inline Subcircuits that enable a circuit
designer to model and Simulate circuits that when compared to conventional System and …

Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure

BW Mcgaughy - US Patent 7,328,143, 2008 - Google Patents
(54) SYSTEMS AND METHODS FOR 6,148,433 A* 1 1/2000 Chowdhary et al............ T16. 1
EFFICIENTLY SIMULATING ANALOG 6,381,563 B1* 4/2002 O'Riordan et al............ TO3/14 …

Symbolic analysis of electrical circuits for application in telecommunications

A Fertner, E Luppert - US Patent App. 10/628,578, 2005 - Google Patents
Abstract Analysis of an electrical circuit is performed using a computer program product (60)
and a method. In accordance with the program and the method, a electrical circuit analyzer …

Self adjusting linear MOSFET simulation techniques

D Stanley, A Trivedi - US Patent App. 10/235,213, 2004 - Google Patents
(57) ABSTRACT A method of circuit Simulation of an overall circuit including at least one
nonlinear component and a plurality of fixed linear components. The process begins by …