Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for
analysis, characterization, estimation, and optimization of the various forms of power …

In this paper, we propose an application-driven ALU design methodology to achieve high
level of power efficiency for modern microprocessors. We introduce a PN selection algorithm …

For a nanoCMOS of sub-65mn technology, where the gate oxide (SiO/sub 2/) thickness is
very low, the gate leakage is one of the major components of power dissipation. In this …

Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology
based integrated circuits for numerous reasons, including improving battery life of the …

The authors present minimization methodologies and an algorithm for simultaneous
scheduling, binding, and allocation for the reduction of total power and power fluctuation …

The authors present two polynomial time-complexity heuristic algorithms for optimisation of
gate-oxide leakage (tunnelling current) during behavioural synthesis through simultaneous …

For CMOS technologies below 65nm, gate oxide direct tunneling current is a major
component of the total power dissipation. This paper presents a simulated annealing based …

Abstract The User Guided Synthesis approach targets the generation of coprocessor under
timing and resource constraints. Unlike other approaches that discover the architecture …

The design space for nanoscale CMOS circuits is vast, with multiple dimensions
corresponding to process variability, leakage, power, thermal, reliability, security, and yield …

As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has
become a major component of total power dissipation. Use of dielectrics of higher …