Superpin: Parallelizing dynamic instrumentation for real-time performance

S Wallace, K Hazelwood - International Symposium on Code …, 2007 - ieeexplore.ieee.org
Dynamic instrumentation systems have proven to be extremely valuable for program
introspection, architectural simulation, and bug detection. Yet a major drawback of modern …

An enhancement of crosstalk avoidance code based on fibonacci numeral system for through silicon vias

X Cui, X Cui, Y Ni, M Miao… - IEEE Transactions on Very …, 2017 - ieeexplore.ieee.org
Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-
D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk …

Transient error correction coding scheme for reliable low power data link layer in NoC

M Vinodhini, NS Murty, TK Ramesh - IEEE Access, 2020 - ieeexplore.ieee.org
Ensuring reliable data transmission in multicore System on Chip (SoC), which employs
Network on Chip (NoC), is a challenging task. This task is well addressed by Error …

An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication

M Ibrahim, NK Baloch, S Anjum… - Software: Practice …, 2021 - Wiley Online Library
Soft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause
hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error …

An efficient numerical-based crosstalk avoidance codec design for NoCs

Z Shirmohammadi, F Mozafari, SG Miremadi - Microprocessors and …, 2017 - Elsevier
With technology scaling, crosstalk fault has become a serious problem in reliable data
transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on …

Crosstalk aware transient error correction coding technique for NoC links

M Vinodhini, NS Murty, TK Ramesh - Microelectronics Reliability, 2021 - Elsevier
Abstract In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect
design are to meet the performance, power consumption requirements of the SoC and to …

Joint crosstalk avoidance with multiple bit error correction coding technique for NoC interconnect

TS Teja, TS Kiran, TVVS Narayana… - … on Advances in …, 2018 - ieeexplore.ieee.org
In an On-chip communication where the devices have scaled down to nanometer scale, a
single chip contains numerous processing elements and inter-communication between …

RETRACTED ARTICLE: Crosstalk minimization in network on chip (NoC) links with dual binary weighted code CODEC

B Subramaniam, S Muthusamy, G Gengavel - Journal of Ambient …, 2021 - Springer
A number of bus encoding techniques are renowned in low power dissipation of network-on-
chip. The objective of the proposed algebraic framework dual binary weighted code (DBWC) …

A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend

X Weng, X Lin, Y Liu, C Xu, L Zhan, S Wang, D Chen… - Micromachines, 2023 - mdpi.com
Network on chip (NoC) is the main solution to the communication bandwidth of a multi-
processor system on chip (MPSoC). NoC also brings more route requirements and is highly …

Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects

AK Chlaab, WN Flayyih, FZ Rokhani - Bulletin of Electrical Engineering and …, 2020 - beei.org
In this paper, we present multiple bit error correction coding scheme based on extended
Hamming product code combined with type II HARQ using shared resources for on chip …