A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL
simulation environment often creates a barrier for those who are not field-programmable …

This work presents a methodology that parallelizes the simulation of mixed-abstraction level
SystemC models across multicore CPUs, and graphics processing units (GPUs) for …

In this article, we developed a massively parallel gate-level logical simulator to address the
ever-increasing computing demand for VLSI verification. To the best of the authors' …

Virtual platforms have become essential tools in the design process of modern embedded
systems. Their accessibility and early availability make them ideal tools for design space …

With the fast increasing complexity of integrated circuits, verification has become the
bottleneck of today's IC design flow. In fact, over 70% of the IC design turn-around time can …

SystemC is a widespread language for HW/SW system simulation and design exploration,
and thus a key development platform in embedded system design. However, the growing …

High-level synthesis (HLS) is a well-established framework used to translate high-level
algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major …

The validation of system models at the transaction-level typically relies on discrete event
(DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) …

Simulation speed is crucial in virtual platforms, in order to enhance the design flow with early
validation and design space exploration. This work tackles this challenge by focusing on two …

Developing complex technical systems requires a systematic exploration of the given design
space in order to identify optimal system configurations. However, studying the effects and …