A multilevel synchronized optical pulsed modulation for high efficiency biotelemetry

GDP Stanchieri, A De Marcellis… - … Circuits and Systems, 2022 - ieeexplore.ieee.org
The paper describes the design, implementation, and characterization of a novel multilevel
synchronized pulse position modulation paradigm for high efficiency optical biotelemetry …

Power Awareness in Low Precision Neural Networks

NS Eliezer, R Banner, H Ben-Yaakov, E Hoffer… - … on Computer Vision, 2022 - Springer
Existing approaches for reducing DNN power consumption rely on quite general principles,
including avoidance of multiplication operations and aggressive quantization of weights and …

Dynamic thermal management for 3-D ICs with time-dependent power map using microchannel cooling and machine learning

YS Li, H Yu, H Jin, TE Sarvey, H Oh… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
It is agreed that air-cooled heat sink (ACHS) would become incapable of 3-D integrated
circuits (ICs). A switch from ACHS to a microfluidic heat sink (MFHS) is believed to be a …

Digitization algorithms in ring oscillator physically unclonable functions as a main factor achieving hardware security

G Diez-Senorans, M Garcia-Bosque… - IEEE …, 2021 - ieeexplore.ieee.org
Since the discovery of the physical random functions and their subsequent refinement into
physical unclonable functions (PUF), a great effort has been made in developing and …

Implementation and Analysis on 4x4 Multiplier using Genesys FPGA Board

S Shrivastava, A Kaur - 2023 International Conference on …, 2023 - ieeexplore.ieee.org
Some regions across the country are currently experiencing severe energy shortages. The
research and implementation of an efficient 4x4 multiplier using the Vivado software platform …

An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits

Z Lyu, J Shen - Microelectronics Journal, 2024 - Elsevier
Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-
scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA) …

EnergyNN: Energy estimation for neural network inference tasks on DPU

S Goel, M Balakrishnan, R Sen - 2021 31st International …, 2021 - ieeexplore.ieee.org
Convolutional Neural Networks (CNNs) are increasingly becoming popular in embedded
and energy limited mobile applications. Hardware designers have proposed various …

Robustness scan of digital circuits using convolutional neural networks

M Vaziri, MM Rahimifar… - 2022 12th International …, 2022 - ieeexplore.ieee.org
Hardware Trojan (HT) is a crucial problem in the integrated circuits and digital systems
industry, which has many malicious impacts on circuits such as overheating, functionality …

Power modeling on FPGA: A neural model for RT-level power estimation

Y Nasser, JC Prévotet, M Hélard - Proceedings of the 15th ACM …, 2018 - dl.acm.org
Today reducing power consumption is a major concern especially when it concerns small
embedded devices. Power optimization is required all along the design flow but particularly …

Early Power Estimation of FPGA-based Digital Transparent Processors for 5G-satcom

G Battisti, G Marini, V Sulli, C Rinaldi… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
As the cost of pure terrestrial coverage will be likely unbearable with increasing capacity
needs for rural, remote, and even urban areas, satellite communications are envisaged to …