Chip design with machine learning: a survey from algorithm perspective
Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …
Llm4eda: Emerging progress in large language models for electronic design automation
Driven by Moore's Law, the complexity and scale of modern chip design are increasing
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …
Machine learning for FPGA electronic design automation
A Biscontini, E Popovici, A Temko - IEEE Access, 2024 - ieeexplore.ieee.org
In the last decades, field-programmable gate arrays (FPGAs) have become increasingly
important to the electronics industry, offering higher performance and lower power …
important to the electronics industry, offering higher performance and lower power …
AlphaSyn: Logic synthesis optimization with efficient monte carlo tree search
Recent years have seen rising research in logic synthesis recipe generation to improve the
Quality-of-Result (QoR). However, existing approaches typically have low efficiency and are …
Quality-of-Result (QoR). However, existing approaches typically have low efficiency and are …
[HTML][HTML] 基于机器学习的FPGA 电子设计自动化技术研究综述
田春生， 陈雷， 王源， 王硕， 周婧， 庞永江， 杜忠 - 电子与信息学报, 2023 - jeit.ac.cn
随着后摩尔时代的来临, 现场可编程门阵列(FPGA) 凭借其灵活的重复可编程特性,
开发成本低的特点, 现已被广泛应用于物联网(IoTs), 5G 通信, 航空航天以及武器装备等各个领域 …
开发成本低的特点, 现已被广泛应用于物联网(IoTs), 5G 通信, 航空航天以及武器装备等各个领域 …
EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning
Logic synthesis tools synthesize circuit structures to optimize specific targets given
reasonable constraints and runtime using a set of well-defined operators. The efficiency of …
reasonable constraints and runtime using a set of well-defined operators. The efficiency of …
Framework and benchmarks for combinatorial and mixed-variable Bayesian optimization
K Dreczkowski, A Grosnit… - Advances in Neural …, 2024 - proceedings.neurips.cc
This paper introduces a modular framework for Mixed-variable and Combinatorial Bayesian
Optimization (MCBO) to address the lack of systematic benchmarking and standardized …
Optimization (MCBO) to address the lack of systematic benchmarking and standardized …
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry
BLC Barzen, A Reais-Parsi, E Hung… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
Historically, open-source FPGA synthesis and technology mapping tools have been
considered far inferior to industry-standard tools. We show that this is no longer true …
considered far inferior to industry-standard tools. We show that this is no longer true …
Enhancing Delay-Driven LUT Mapping With Boolean Decomposition
AT Calvino, G De Micheli… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to
map combinational logic into lookup tables (LUTs) structures when synthesizing hardware …
map combinational logic into lookup tables (LUTs) structures when synthesizing hardware …
Optimistic tree searches for combinatorial black-box optimization
The optimization of combinatorial black-box functions is pervasive in computer science and
engineering. However, the combinatorial explosion of the search space and lack of natural …
engineering. However, the combinatorial explosion of the search space and lack of natural …