The purpose of this monograph is to provide both an introduction to eld of asynchronous
digital circuit design and an overview of the practical state of the art in 1997. In the early …

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The
defect density distributions are similar, and hence, so are the fault models and fault …

Even though the asynchronous design methodology is considered to be a promising
solution to upcoming challenges of designing complex integrated circuits (ICs), it is not …

Volume 38-Supplement 23: Algorithms for Designing Multimedia Storage Servers to Models
and Architectures. Covering more than basic computer commands and procedures, this …

This work introduces a methodology to ease the implementation of BIST in asynchronous
circuits. Scheduling by edge reversal (SER), a simple but powerful distributed synchronizer …

Due to asynchronous timing and arbitration asynchronous designs may behave no
deterministically. For the test of such systems, this means that an exact timing, ie a tester …

Asynchronous interfaces, being a popular way of dealing with timing closure problems in
deep submicron SoCs, pose a serious problem for on-line testing. Their behavior is …

The drive for more power-efficient circuits has been one of the main reasons to search for
alternatives for the conventional synchronous circuit design style. One of the main obstacles …

At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its
timing constraints between control and data paths, Design for Testability (DfT) …

[20] AJ Acosta, R. Jiménez, A. Barriga, MJ Bellido, M. Valencia, and JL Huertas,“Design and
characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level …