Recent research development and new challenges in analog layout synthesis

MPH Lin, YW Chang, CM Hung - 2016 21st Asia and South …, 2016 - ieeexplore.ieee.org
Analog and mixed-signal integrated circuits play an important role in many modern
emerging system-on-chip (SoC) design applications. With the expansion of the markets of …

MAGICAL: Toward fully automated analog IC layout leveraging human and machine intelligence

B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
Despite tremendous advancement of digital IC design automation tools over the last few
decades, analog IC layout is still heavily manual which is very tedious and error-prone. This …

Fast surrogate-assisted constrained multiobjective optimization for analog circuit sizing via self-adaptive incremental learning

S Yin, R Wang, J Zhang, X Liu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, we propose an efficient surrogate-assisted constrained multiobjective
evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The …

LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies

J Han, W Bae, E Chang, Z Wang… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for
enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is …

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

M Liu, W Li, K Zhu, B Xu, Y Lin, L Shen… - 2020 25th Asia and …, 2020 - ieeexplore.ieee.org
Symmetry and matching between critical building blocks have a significant impact on analog
system performance. However, there is limited research on generating system level …

A novel analog physical synthesis methodology integrating existent design expertise

PH Wu, MPH Lin, TC Chen, CF Yeh… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Analog layout design has been a manual, time-consuming, and error-prone task for
decades. To speed up layout design time for a new design, analog layout designers prefer …

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

N Lourenço, R Martins, A Canelas, R Povoa, N Horta - Integration, 2016 - Elsevier
This paper presents AIDA, an analog integrated circuit design automation environment,
which implements a design flow from a circuit-level specification to physical layout …

[图书][B] Automatic analog IC sizing and optimization constrained with PVT corners and layout effects

N Lourenço, R Martins, N Horta - 2017 - Springer
Over the past few decades, very large scale integration technologies have been widely
improved, allowing the proliferation of consumer electronics and enabling the steady growth …

Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop

R Martins, N Lourenço, F Passos… - … on Computer-Aided …, 2018 - ieeexplore.ieee.org
In this paper, an analysis of the methodologies proposed in the past years to automate the
synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this …

An open source compatible framework to fully autonomous digital ldo generation

YK Cherivirala, M Saligane… - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
This work presents an open-source methodology to automate the design and layout of a low
dropout (LDO) regulator from high-level performance specifications. LDO designs with this …