Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification

M Liu, M Kang, GB Hamad, S Suhaib… - 2024 IEEE 42nd VLSI …, 2024 - ieeexplore.ieee.org
Large language models (LLMs) present unprecedented opportunities in task automation for
industrial chip design and verification that can yield significant improvements in engineering …