Low power and area efficient implementation of BCD adder on FPGA

S Mishra, G Verma - 2013 International conference on signal …, 2013 - ieeexplore.ieee.org
Decimal adders and multipliers are the basic building block for arithmetic and logical unit
and barrel shifters in today's high end processors and controllers. In this paper, an efficient …

[PDF][PDF] Low power techniques for digital system design

G Verma, M Kumar, V Khare - Indian Journal of Science and …, 2015 - researchgate.net
The proliferation of reconfigurable hardware like (FPGAs) put a challenge in front of
designers to implement fast and low powered digital designs. Main drawbacks of FPGAs are …

[PDF][PDF] Power consumption analysis of BCD adder using xpower analyzer on VIRTEX FPGA

G Verma, S Mishra, S Aggarwal… - Indian Journal …, 2015 - sciresol.s3.us-east-2.amazonaws …
Adders are the integral part of any digital circuit operation. Optimization of adder's
supremacy along with its vicinity is a demanding chore. In this work an efficient BCD …

Design and analysis of reversible binary and BCD adders

AN Nagamani, NJ Reddy, VK Agrawal - … : Proceedings of ICMEET 2015, 2016 - Springer
Reversible logic in recent times has attracted a lot of research attention in the field of
Quantum computation and nanotechnology due to its low power dissipation capability …

A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme

D Saha, S Basak, S Mukherjee… - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder
design where the conventional 4-bit BCD adder has been modified with the Clock Gated …

An Investigation n Three Operand Binary Adders

R Abinaya, S Lavanya, P Anguraj… - 2022 8th International …, 2022 - ieeexplore.ieee.org
Adder is one of the vital elements in multi-media applications like the Digital Signal
Processor (DSP). Therefore, many researchers have recently been researching optimizing …

[PDF][PDF] Design and implementation of reduced power energy efficient binary coded decimal adder

N Saravanakumar, KS Sudhan… - International …, 2019 - pdfs.semanticscholar.org
This paper presents a novel architecture for low power energy binary represented decimal
addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for …