A generic VHDL template for 2D stencil code applications on FPGAs

M Schmidt, M Reichenbach… - 2012 IEEE 15th …, 2012 - ieeexplore.ieee.org
The efficient realization of self-organizing systems based on 2D stencil code applications,
like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive …

FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler

Z Choudhury, A Gulati, S Purini - ACM Transactions on Architecture and …, 2023 - dl.acm.org
The exponential performance growth guaranteed by Moore's law has started to taper in
recent years. At the same time, emerging applications like image processing demand heavy …

[PDF][PDF] Ipol—a domain specific language for image processing applications

C Hartmann, M Reichenbach… - Proceedings of the …, 2015 - personales.upv.es
In recent years, the use of image processing systems has increased steadily. However, most
of them are very complex and contain several tasks with different complexities which result …

An efficient and compact row buffer architecture on FPGA for real-time neighbourhood image processing

M Kazmi, A Aziz, P Akhtar - Journal of Real-Time Image Processing, 2019 - Springer
This work presents a compact and efficient row buffer (RB) architecture on field-
programmable gate array (FPGA). The design confines multiple RBs within the full capacity …

[图书][B] Parallel Embedded Computing Architectures

M Schmidt, D Fey, M Reichenbach - 2012 - books.google.com
It was around the years 2003 to 2005 that a dramatic change seized the semiconductor
industry and the manufactures of processors. The increasing of computing performance in …

[PDF][PDF] FPGA based compact and efficient full image buffering for neighborhood operations

M Kazmi, A Aziz, P Akhtar, D Kundi - Adv. Electr. Comput. Eng, 2015 - researchgate.net
Neighborhood operations based image pre-processing is frequently used to obtain high
quality output images. These neighborhood operations use two dimensional (2D) structuring …

[PDF][PDF] A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs: ERSA'12 Distinguished Paper

F Richter, M Schmidt, D Fey - Proceedings of the International …, 2012 - world-comp.org
2D and 3D stencil code applications are very common in scientific computing, but their
performance is mostly limited by the memory bandwidth. Elaborate onchip buffering …

Разработка высокопроизводительного параллельного алгоритма масштабирования изображений

ИВ Егоров, АА Внуков - … вычисления и задачи управления PACO'2012, 2012 - elibrary.ru
В статье рассматриваются вопросы, связанные с масштабированием цифровых
изображений, оптимизацией проводимых вычислений путём использования …

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

M Kazmi, A Aziz, HR Khan, SA Qazi… - IEEE Access, 2020 - ieeexplore.ieee.org
Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are
considered as memory intensive operations. A large memory bandwidth is required to …

[图书][B] Evaluierung gitterbasierter Pfadplanungs-Algorithmen für die Hardwarebeschleunigung mit FPGAs

M Schmidt - 2013 - search.proquest.com
Abstract Die Anforderungen an mobile Robotersysteme nehmen stetig zu. Immer mehr
Aufgaben sollen nach Möglichkeit autonom gelöst werden. Die dafür notwendigen …