Interleaving active feedback in inverter-based optical receivers for bandwidth extension and linearity improvement

S Radfar, G Cowan - 2024 IEEE International Symposium on …, 2024 - ieeexplore.ieee.org
Main amplifiers are crucial components in the design of optical receivers, amplifying the
output voltage of the transimpedance amplifier (TIA). While Cherry-Hooper (CH) amplifiers …

[图书][B] System-driven circuit design for ADC-based wireline data links

K Zheng - 2018 - search.proquest.com
In the era of connectivity, wireline I/O has been a key technology underpinning the
aggressive performance improvements of computer and communication systems. All …

Time dependent line equalizer for data transmission systems

T Beukema - US Patent 10,812,301, 2020 - Google Patents
A dynamic tap weight generator circuit includes a clock generator circuit having a first output
and a second output. There is a current interpolator circuit coupled to a first current source …

Transmitter equalization optimization for ethernet chip-to-module (C2M) compliance

G Tomer, AO Ran, L Brecher, E Nussbaum - US Patent 12,113,651, 2024 - Google Patents
Techniques and apparatus for optimizing transmitter equalization are described. An
example technique includes capturing a single output signal transmitted from a port on at …

Method and wire-line transceiver for performing serial loop back test

V Khatri, T Das, UR Katta - US Patent 11,979,263, 2024 - Google Patents
A wire-line transceiver is configured to perform a serial loop back test. The wire-line
transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward …

Time dependent line equalizer for data transmission systems

T Beukema - US Patent 12,081,642, 2024 - Google Patents
A data equalization system includes a data clock input configured to receive a clock signal.
There is an input node operative to receive a data signal of transmission symbols that …