Review of neural network model acceleration techniques based on FPGA platforms

F Liu, H Li, W Hu, Y He - Neurocomputing, 2024 - Elsevier
Neural network models, celebrated for their outstanding scalability and computational
capabilities, have demonstrated remarkable performance across various fields such as …

Compact and robust deep learning architecture for fluorescence lifetime imaging and FPGA implementation

Z Zang, D Xiao, Q Wang, Z Jiao, Y Chen… - … and Applications in …, 2023 - iopscience.iop.org
Compact and robust deep learning architecture for fluorescence lifetime imaging and FPGA
implementation - IOPscience Skip to content IOP Science home Accessibility Help Search …

Electronic nose pattern recognition engine: Design, build, and deployment

F Sun, B Wu, J Yan, S Duan, X Hu - IEEE Sensors Journal, 2022 - ieeexplore.ieee.org
The electronic nose (e-nose) consists of a sensor array, a pattern recognition engine, and
peripheral circuitry, where the pattern recognition engine performs gas classification. The …

Method for accelerating operations and accelerator apparatus

G Nagy, M Fehér, IH Weimann - US Patent App. 17/048,048, 2021 - Google Patents
A method for accessing and processing data by an accelera tor apparatus includes
retrieving at least a part of input data to be processed by the accelerator apparatus …

Hardware Design of Lightweight Binary Classification Algorithms for Small-Size Images on FPGA

S Saglam, S Bayar - IEEE Access, 2024 - ieeexplore.ieee.org
This study explores the implementation of lightweight binary classification algorithms on low-
cost Field-Programmable Gate Arrays (FPGAs) for medical image analysis. Recognizing the …

Minimal filtering algorithms for convolutional neural networks

A Cariow, G Cariowa - Reliability Engineering and Computational …, 2021 - Springer
In this paper, we present several resource-efficient algorithmic solutions regarding the fully
parallel hardware implementation of the basic filtering operation performed in the …

[PDF][PDF] 동적저궤도위성네트워크에서온보드강화학습기반라우팅을위한이종프로세서기반추론병렬화기술

김도형, 이민준, 이헌철, 원동식, 한명훈 - 한국정보기술학회논문지, 2023 - ki-it.com
요 약본 논문에서는 동적 저궤도 위성 네트워크 라우팅 알고리즘의 OBC (On-Board Computer)
적용 문제를 다룬다. 저궤도 위성 간 연결상태가 동적으로 변하는 네트워크에서 라우팅을 위해 …

[PDF][PDF] GENERIC DESIGN FLOW OF PIPELINED HARDWARE IMPLEMENTATION OF DEEP NEURAL NETWORKS

M Eleuldj - ijcse.com
Abstract DNNs (Deep Neural Networks) have solved various deep learning tasks, including
classification problems, natural language processing, and speech recognition. However, this …

[PDF][PDF] Сравнение производительности инференсов сверточных нейронных сетей на GPU и FPGA

ЕС Дергунов, АК Берзин - 2021 - vital.lib.tsu.ru
Глубокое обучение, отрасль машинного обучения, ориентированная на использование
искусственных нейронных сетей, является одной из самых востребованных и …

Arithmetic device

K Suwabe, K Sugihara, S Takeda - US Patent App. 17/049,065, 2021 - Google Patents
An arithmetic device includes a first register that stores input data as values of a plurality of
input neurons, a plurality of ports, and a plurality of processing element groups that …