Misleading worm signature generators using deliberate noise injection

R Perdisci, D Dagon, W Lee, P Fogla… - 2006 IEEE Symposium …, 2006 - ieeexplore.ieee.org
Several syntactic-based automatic worm signature generators, eg, Polygraph, have recently
been proposed. These systems typically assume that a set of suspicious flows are provided …

Run-time resource management controller for power efficiency of GP-GPU architecture

S Najam, J Ahmed, S Masood, CM Ahmed - IEEE Access, 2019 - ieeexplore.ieee.org
The demand for high-performance computing (HPC) has been increasing since the
invention of computing technology. This led to the invocation of sophisticated multi/many …

Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs

MY Qadri, KD McDonald Maier… - Journal of Intelligent & …, 2014 - content.iospress.com
Multicore architectures offer an amount of parallelism that is often underutilized, as a result
these underutilized resources become a liability instead of advantage. Inefficient resource …

Automatic software hardware co-design for reconfigurable computing systems

P Saha - … Conference on Field Programmable Logic and …, 2007 - ieeexplore.ieee.org
A formal methodology for automatic hardware-software partitioning and co-scheduling
between the muP and the field programmable gate array (FPGA) has not yet been …

Software/hardware co-scheduling for reconfigurable computing systems

P Saha, T El-Ghazawi - 15th Annual IEEE Symposium on Field …, 2007 - ieeexplore.ieee.org
A formal methodology for automatic hardware-software partitioning and co-scheduling
between the P and the FPGA has not yet been established. Current work in automatic task …

A methodology for automating co-scheduling for reconfigurable computing systems

P Saha, T El-Ghazawi - … on Formal Methods and Models for …, 2007 - ieeexplore.ieee.org
A formal methodology for automatic hardware-software partitioning and co-scheduling
between the muP and the FPGA has not yet been established. Current work in automatic …

Scheduling task graphs on heterogeneous multiprocessors with reconfigurable hardware

J Teller, F Özgüner, R Ewing - 2008 International Conference …, 2008 - ieeexplore.ieee.org
We address the problem of scheduling applications represented as directed acyclic task
graphs (DAGs) onto architectures with reconfigurable processing cores. We introduce the …

[PDF][PDF] A novel methodology for task distribution in heterogeneous reconfigurable computing system

M Vucha, A Rajawat - International Journal of Embedded Systems …, 2015 - researchgate.net
Modern embedded systems are being modeled as Heterogeneous Reconfigurable
Computing Systems (HRCS) where Reconfigurable Hardware ie Field Programmable Gate …

Dynamic Task Distribution Model for On‐Chip Reconfigurable High Speed Computing System

M Vucha, A Rajawat - International Journal of Reconfigurable …, 2015 - Wiley Online Library
Modern embedded systems are being modeled as Reconfigurable High Speed Computing
System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array …

A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors

MY Qadri, KD McDonald-Maier - 2010 NASA/ESA Conference …, 2010 - ieeexplore.ieee.org
Embedded systems architectures have traditionally often been investigated and designed in
order to achieve a greater throughput combined with minimum energy consumption. With …