Designs of two quadruple-node-upset self-recoverable latches for highly robust computing in harsh radiation environments
This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …
LDAVPM: A latch design and algorithm-based verification protected against multiple-node-upsets in harsh radiation environments
In deep nano-scale and high-integration CMOS technologies, storage circuits have become
increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include …
increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include …
Two double-node-upset-hardened flip-flop designs for high-performance applications
The continuous advancement of complementary metal-oxide-semiconductor technologies
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
A radiation-hardened CMOS full-adder based on layout selective transistor duplication
Single event transients (SETs) have become increasingly problematic for modern CMOS
circuits due to the continuous scaling of feature sizes and higher operating frequencies …
circuits due to the continuous scaling of feature sizes and higher operating frequencies …
A soft error detection and recovery flip-flop for aggressive designs with high-performance
J Li, L Xiao, H Li, X Cao, C Wang - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great
threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits …
threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits …
R2F: A remote retraining framework for AIoT processors with computing errors
Artificial Intelligence of Things (AIoT) processors fabricated with newer technology nodes
suffer rising soft errors due to the shrinking transistor sizes and lower power supply. Soft …
suffer rising soft errors due to the shrinking transistor sizes and lower power supply. Soft …
A low-cost error-tolerant flip-flop against SET and SEU for dependable designs
J Li, L Xiao, L Li, H Li, H Liu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Computing systems working in harsh environment is prone to suffer from radiation-induced
soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are …
soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are …
[HTML][HTML] System-on-chip single event effect hardening design and validation using proton irradiation
A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-
Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system …
Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system …
Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm based Verifications
With the aggressive shrinking of transistor feature sizes, nano-scale CMOS circuits are
becoming more vulnerable to multi-node-upsets, eg, triple-node-upsets (TNUs) as well as …
becoming more vulnerable to multi-node-upsets, eg, triple-node-upsets (TNUs) as well as …
A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design
S Cai, J Ouyang, Y Wen, W Wang… - 2023 IEEE 32nd Asian …, 2023 - ieeexplore.ieee.org
With the continuous shrinking of the size of the semiconductor process, the multi-node upset
(MNU) brought about by the charge-sharing effect in the nano-integrated circuit has a huge …
(MNU) brought about by the charge-sharing effect in the nano-integrated circuit has a huge …