Design automation of series resonance clocking in 14-nm FinFETs

D Challagundla, I Bezzam, R Islam - Circuits, Systems, and Signal …, 2023 - Springer
Power-performance constraints have been the key driving force that motivated the
microprocessor industry to bring unique design techniques in the past two decades. The …

Resonant energy recycling sram architecture

R Islam, B Saha, I Bezzam - … on Circuits and Systems II: Express …, 2020 - ieeexplore.ieee.org
Although we may be at the end of Moore's law, lowering chip power consumption is still the
primary driving force for the designers. To enable low-power operation, we propose a …

Low-power highly reliable SET-induced dual-node upset-hardened latch and flip-flop

R Islam - Canadian Journal of Electrical and Computer …, 2019 - ieeexplore.ieee.org
It appears that the relentless pursuit of Moore's law scaling from one generation of process
technology to the next increases circuit vulnerability to single-event transient (SET)-induced …

Power and skew reduction using resonant energy recycling in 14-nm FinFET clocks

D Challagundla, M Galib, I Bezzam… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
As the demand for high-performance microprocessors increases, the circuit complexity and
the rate of data transfer increases resulting in higher power consumption. We propose a …

[PDF][PDF] Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

SE Esmaeili, A Imdoukh - Indian Journal …, 2021 - sciresol.s3.us-east-2.amazonaws …
Abstract Background/Objectives: Density, performance, and design complexity of integrated
circuits are rapidly increasing specifically in 3-D integration where multi-plane …

High-speed on-chip signaling: Voltage or current-mode?

R Islam - IETE Journal of Research, 2021 - Taylor & Francis
In this paper, we investigate several on-chip signaling schemes. Specifically, we compare
different voltage-mode (VM) and current-mode (CM) signaling schemes considering power …

A SEU Immune Flip-Flop with Low Overhead

Z Huang, X Li, S Pan, M Wang, T Ni - International Conference on …, 2020 - Springer
In nano-scale CMOS technologies, storage cells such as flip-flops are becoming
increasingly sensitive to soft errors caused by harsh radiation effects. This paper proposes a …