Machine-learning circuit optimization using quantized prediction functions

N Oh - US Patent 10,817,634, 2020 - Google Patents
An EDA tool trains a machine-learning optimization tool using quantized optimization
solution (training) data generated by conventional optimization tools. Each training data …

Parasitic extraction in an integrated circuit with multi-patterning requirements

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2014 - Google Patents
Abstract Systems and methods are provided for extracting parasitics in a design of an
integrated circuit with multi-patterning requirements. The method includes determining …

Hierarchical design of integrated circuits with multi-patterning requirements

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2014 - Google Patents
2012-10-31 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …

Modeling multi-patterning variability with statistical timing

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2015 - Google Patents
BACKGROUND An IC is a device (eg, a semiconductor device) or elec tronic system that
includes many electronic components, such as transistors, resistors, diodes, etc. These …

Modeling multi-patterning variability with statistical timing

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2014 - Google Patents
Abstract Systems and methods for modeling multi-patterning variability with statistical timing
analysis during IC fabrication are described. The method may be provided implemented in a …

Parasitic extraction in an integrated circuit with multi-patterning requirements

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2015 - Google Patents
BACKGROUND An IC is a device (eg, a semiconductor device) or elec tronic system that
includes many electronic components, Such as transistors, resistors, diodes, etc. These …

System, method, and computer program product for predicting parasitics in an electronic design

S Bhushan, EL Fallon, C Ahuja - US Patent 11,620,548, 2023 - Google Patents
US11620548B1 - System, method, and computer program product for predicting parasitics in an
electronic design - Google Patents US11620548B1 - System, method, and computer program …

Modeling multi-patterning variability with statistical timing

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2016 - Google Patents
BACKGROUND An IC is a device (eg, a semiconductor device) or elec tronic system that
includes many electronic components, Such as transistors, resistors, diodes, etc. These …

Hierarchical design of integrated circuits with multi-patterning requirements

N Buck, B Dreibelbis, JP Dubuque… - US Patent …, 2016 - Google Patents
Abstract Systems and methods for avoiding restrictions on cell placement in a hierarchical
design of integrated circuits with multi-patterning requirements are described. The method …

Constraint determination system and method for semiconductor circuit

YL Chuang, TAN Shi-Wen, SJ Huang… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A method, for determining constraints related to a target circuit, includes
following operations. First circuit speed results of the target circuit under different candidate …