The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …

With increased inter-connectivity among disparate devices, such as Internet-of-Things (IoT)
devices, including those deployed in a nation's critical infrastructure, there is a need to …

In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-
adaptation capability against aging-induced degradation. The proposed flow utilizes the …

This paper proposes a novel methodology to design high reliable STT-MRAM, with self-
activated built-in-self-test (BIST) against aging/temperature-induced degradation. During …

Many wireless networks are susceptible to spoofing attacks, whereby an adversary imitates
the network identifiers of legitimate devices. Conventionally, assuring the identity of the …

CMOS technology scaling makes aging effects an important concern for the design and
fabrication of integrated circuits. Aging deterioration reduces the useful life of a circuit …

In this paper, we present a novel methodology, BIST-RM, to accurately predict the
degradation due to aging mechanisms in a SoC at run-time by utilizing the existing LBIST …

Thanks to advances in semiconductor and communication technologies, a multitude of
devices can be connected over a network. This widespread interconnectivity among …

With the rapid reduction in the size of chips nowadays, the phenomenon of circuit aging is
becoming more significant. The impact of circuit aging includes slower chip speed, irregular …

Time-variant age information of different parts of a system can be used for system-level
performance improvement through high-level task scheduling, thus extending the life-time of …