A 0.1–2-GHz quadrature correction loop for digital multiphase clock generation circuits in 130-nm CMOS
I Raja, V Khatri, Z Zahir… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital
clocks is presented. The proposed circuit consists of a phase-locked looptype architecture …
clocks is presented. The proposed circuit consists of a phase-locked looptype architecture …
A Commutated-LC RF Broadband Delay Circuit
This article presents a commutated-inductor–capacitor (commutated-) or switched-circuit that
acts as a radio frequency (RF) delay line. Thanks to its linear-periodically time-varying …
acts as a radio frequency (RF) delay line. Thanks to its linear-periodically time-varying …
A 50–1600 MHz wide–range digital duty–cycle corrector with counter–based half–cycle delay line
Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or
if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a …
if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a …
Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process
HW Kim, S Kim, KY Lee - Electronics, 2023 - mdpi.com
In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets,
a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock …
a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock …
A delay cell with duty-cycle correction and parasitic compensation for large array indirect time-of-flight CMOS image sensors
Large array indirect time-of-flight (ToF) CMOS image sensors use a self-compensating
voltage-controlled delay line (VCDL) to decrease the peak current of the demodulation …
voltage-controlled delay line (VCDL) to decrease the peak current of the demodulation …
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation
On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT
and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques …
and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques …
A 0.75–2.5-GHz All-Digital RF Transmitter With Integrated Class-E Power Amplifier for Spectrum Sharing Applications in 5G Radios
I Raja, G Banerjee - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
We propose a digitally intensive, reconfigurable RF transmitter with an integrated, tunable
Class-E power amplifier (PA) which can be configured to operate from 0.75 to 2.5 GHz in …
Class-E power amplifier (PA) which can be configured to operate from 0.75 to 2.5 GHz in …
A low-power and area-efficient analog duty cycle corrector for ADC's external clocks
N Liu, J Todsen, D Chen - 2020 IEEE International Symposium …, 2020 - ieeexplore.ieee.org
This paper presents an analog duty cycle corrector with feedback. A differential charge
pump with fast startup is used to detect the duty cycle error and outputs a control voltage for …
pump with fast startup is used to detect the duty cycle error and outputs a control voltage for …
A 0.35 μm CMOS 200kHz–2GHz Fully-Analogue Closed-Loop Circuit for Continuous-Time Clock Duty-Cycle Correction in Integrated Digital Systems
A De Marcellis, M Faccio… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
In this work we present a fully-analogue Duty-Cycle Corrector (DCC) based on a closed-
loop circuit topology operating a continuous-time 50% duty-cycle regulation of the generated …
loop circuit topology operating a continuous-time 50% duty-cycle regulation of the generated …
A duty cycle corrector with dual loop low pass filter for low jitter and fast correction time
EY Jung, WY Lee - AEU-International Journal of Electronics and …, 2023 - Elsevier
In this paper, a duty cycle corrector (DCC) with a dual loop low pass filter (DLLPF) has been
proposed to improve correction time and noise characteristics. It shows that the correction …
proposed to improve correction time and noise characteristics. It shows that the correction …