Pond: Cxl-based memory pooling systems for cloud platforms
Public cloud providers seek to meet stringent performance requirements and low hardware
cost. A key driver of performance and cost is main memory. Memory pooling promises to …
cost. A key driver of performance and cost is main memory. Memory pooling promises to …
Drisa: A dram-based reconfigurable in-situ accelerator
Data movement between the processing units and the memory in traditional von Neumann
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
Memory isolation is a key property of a reliable and secure computing system--an access to
one memory address should not have unintended side effects on data stored in other …
one memory address should not have unintended side effects on data stored in other …
Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications
The RowHammer vulnerability in DRAM is a critical threat to system security. To protect
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
AVATAR: A variable-retention-time (VRT) aware refresh for DRAM systems
Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …
[PDF][PDF] Research problems and opportunities in memory systems
O Mutlu, L Subramanian - Supercomputing frontiers and …, 2014 - superfri.susu.ru
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …
computing systems. Recent system design, application, and technology trends that require …
Scalable and secure row-swap: Efficient and safe row hammer mitigation in memory systems
As Dynamic Random Access Memories (DRAM) scale, they are becoming increasingly
susceptible to Row Hammer. By rapidly activating rows of DRAM cells (aggressor rows) …
susceptible to Row Hammer. By rapidly activating rows of DRAM cells (aggressor rows) …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …