Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
Rapid developments in semiconductor technology have substantially increased the
computational capability of computers. As a result of this and recent developments in theory …
computational capability of computers. As a result of this and recent developments in theory …
A comprehensive survey on electronic design automation and graph neural networks: Theory and applications
Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design
Automation (EDA) has been able to cope with the challenging very large-scale integration …
Automation (EDA) has been able to cope with the challenging very large-scale integration …
GANA: Graph convolutional network based automated netlist annotation for analog circuits
K Kunal, T Dhar, M Madhusudan… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Automated subcircuit identification and annotation enables the creation of hierarchical
representations of analog netlists, and can facilitate a variety of design automation tasks …
representations of analog netlists, and can facilitate a variety of design automation tasks …
MAGICAL: Toward fully automated analog IC layout leveraging human and machine intelligence
Despite tremendous advancement of digital IC design automation tools over the last few
decades, analog IC layout is still heavily manual which is very tedious and error-prone. This …
decades, analog IC layout is still heavily manual which is very tedious and error-prone. This …
ALIGN: A system for automating analog layout
ALIGN: A System for Automating Analog Layout Page 1 8 2168-2356/20©2020 IEEE
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test …
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC IEEE Design&Test …
MAGICAL: An open-source fully automated analog IC layout system from netlist to GDSII
MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII
Page 1 2168-2356 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution …
Page 1 2168-2356 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution …
A general approach for identifying hierarchical symmetry constraints for analog circuit layout
Analog layout synthesis requires some elements in the circuit netlist to be matched and
placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile …
placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile …
Fast surrogate-assisted constrained multiobjective optimization for analog circuit sizing via self-adaptive incremental learning
S Yin, R Wang, J Zhang, X Liu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, we propose an efficient surrogate-assisted constrained multiobjective
evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The …
evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The …
LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies
LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for
enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is …
enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is …
Opportunities and challenges of graph neural networks in electrical engineering
Graph neural networks (GNNs) are a class of deep learning algorithms that learn from
graphs, networks and relational data. They have found applications throughout the sciences …
graphs, networks and relational data. They have found applications throughout the sciences …