H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …

Associating working sets and threads is disclosed. An indication of a stalling event is
received. In response to receiving the indication of the stalling event, a state of a processor …

Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a
computer system. Each node includes a plurality of processors. Each processor includes a …

H04L 29/08(2006.01) GO6F 3/40(2006.01)(57) ABSTRACT GO6F 3/28(2006.01)
Embodiments of the present invention are directed to memo GO6F 3/42(2006.01) ries used …

Maintaining cache coherency in the presence of a network attached memory is disclosed. A
computer system includes a plurality of physical nodes. An operating system is run …

Aspects include creating a network multicast group in a storage area network (SAN) for a
first computer system and a second computer system that are connected by the SAN and …

A data processing system, having two or more of processors that access a shared data
resource, and method of operation thereof. Data stored in a local cache is marked as being …

A method for identifying, in a system including two or more computing devices that are able
to communicate with each other, with each computing device having with a cache and …

Entanglement of pages and threads is disclosed. An indication is received of a stalling event
caused by a requested portion of memory being inaccessible. It is determined that the …

Techniques and mechanisms for providing a shared memory which spans an interconnect
fabric coupled between com pute nodes. In an embodiment, a field-programmable gate …