Survey of scheduling techniques for addressing shared resources in multicore processors

S Zhuravlev, JC Saez, S Blagodurov… - ACM Computing …, 2012 - dl.acm.org
Chip multicore processors (CMPs) have emerged as the dominant architecture choice for
modern computing platforms and will most likely continue to be dominant well into the …

Modeling virtual machine performance: challenges and approaches

O Tickoo, R Iyer, R Illikkal, D Newell - ACM SIGMETRICS Performance …, 2010 - dl.acm.org
Data centers are increasingly employing virtualization and consolidation as a means to
support a large number of disparate applications running simultaneously on server …

Bubble-flux: Precise online qos management for increased utilization in warehouse scale computers

H Yang, A Breslow, J Mars, L Tang - ACM SIGARCH Computer …, 2013 - dl.acm.org
Ensuring the quality of service (QoS) for latency-sensitive applications while allowing co-
locations of multiple applications on servers is critical for improving server utilization and …

{STEALTHMEM}:{System-Level} protection against {Cache-Based} side channel attacks in the cloud

T Kim, M Peinado, G Mainar-Ruiz - 21st USENIX Security Symposium …, 2012 - usenix.org
Cloud services are rapidly gaining adoption due to the promises of cost efficiency,
availability, and on-demand scaling. To achieve these promises, cloud providers share …

Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches

MK Qureshi, YN Patt - 2006 39th Annual IEEE/ACM …, 2006 - ieeexplore.ieee.org
This paper investigates the problem of partitioning a shared cache between multiple
concurrently executing applications. The commonly used LRU policy implicitly partitions a …

PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms

H Yun, R Mancuso, ZP Wu… - 2014 IEEE 19th Real …, 2014 - ieeexplore.ieee.org
DRAM consists of multiple resources called banks that can be accessed in parallel and
independently maintain state information. In Commercial Off-The-Shelf (COTS) multicore …

Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems

O Mutlu, T Moscibroda - ACM SIGARCH Computer Architecture News, 2008 - dl.acm.org
In a chip-multiprocessor (CMP) system, the DRAM system isshared among cores. In a
shared DRAM system, requests from athread can not only delay requests from other threads …

Stall-time fair memory access scheduling for chip multiprocessors

O Mutlu, T Moscibroda - 40th Annual IEEE/ACM International …, 2007 - ieeexplore.ieee.org
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP)
system. Memory requests from different threads can interfere with each other. Existing …

Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems

E Ebrahimi, CJ Lee, O Mutlu, YN Patt - ACM Sigplan Notices, 2010 - dl.acm.org
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the
memory subsystem. If resource sharing is unfair, some applications can be delayed …

The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory

L Subramanian, V Seshadri, A Ghosh, S Khan… - Proceedings of the 48th …, 2015 - dl.acm.org
In a multi-core system, interference at shared resources (such as caches and main memory)
slows down applications running on different cores. Accurately estimating the slowdown of …