Abstract Network on Chip (NoC) is an interesting technology that benefits from several
processing elements and the necessary communication facilities, to provide an answer to …

Network-on-Chip (NoC) technology has emerged as a critical innovation in the field of
integrated circuit design, addressing the growing demands for efficient, scalable, and high …

Innovative processor architecture designs are shifting towards Many-Core Architectures
(MCAs) to meet the future demands of high-performance computing as the limits of Moore's …

Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-
performance multicore computing and network system architectures. Its adoption has …

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its
performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally …

This paper presents three on-chip interconnection techniques that alleviate the performance
degradation issues caused by continuous scaling of global interconnect parameters. The …

In this work, the circulant topology as an alternative to 2D mesh in networks-on-chip is
considered. A virtual coordinate system for numbering nodes in the circulant topology is …

This article describes a hardware and software complex for prototyping networks on a chip
(NoCs) using multiple FPGAs. The rationale for using FPGAs to verify the RTL model of …

Canonical ensembles of walks in a finite connected graph assign the properly normalized
probability distributions to all nodes, subgraphs, and nodal subsets of the graph at all time …

Heterogeneous architectures are vastly used in various high performance computing
systems from IoT‐based embedded architectures to edge and cloud systems. Although …